A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.

This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.

In this paper, a new transceiver system for the in-vehicle communication system is proposed to enhance data transmission rate and timing accuracy in TDM-based application. The proposed system utilizes point-to-point (P2P) channel, a closed-loop clock forwarding path, and a transceiver with a repeater and clock delay adjuster. The proposed system with 4 ECU (Electronic Computing Unit) nodes is implemented in 180nm CMOS technology and, when compared with conventional bus-based system, achieved more than 125 times faster data transmission. The maximum data rate was 2.5Gbps at 1.8V power supply and the worst peak-to-peak jitter for the data and clock signals over 5000 data symbols were about 49.6ps and 9.8ps respectively.

Constrained by quality-of-service (QoS), a robust transceiver design is proposed for multiple-input multiple-output (MIMO) interference channels with imperfect channel state information (CSI) under bounded error model. The QoS measurement is represented as the signal-to-interference-plus-noise ratio (SINR) for each user with single data stream. The problem is formulated as sum power minimization to reduce the total power consumption for energy efficiency. In a centralized manner, alternating optimization is performed at each node. For fixed transmitters, closed-form expression for the receive beamforming vectors is deduced. And for fixed receivers, the sum-power minimization problem is recast as a semi-definite program form with linear matrix inequalities constraints. Simulation results demonstrate the convergence and robustness of the proposed algorithm, which is important for practical applications in future wireless networks.

This paper describes transmission line couplers for non-contact connecters. Their characteristics are formulated in closed forms and design methodologies are presented. As their applications, three different types of transmission line couplers, two-fold transmission line coupler, single-ended to differential conversion transmission line coupler, and rotatable transmission line coupler are reviewed.

Ethernet has become an indispensable technology for communications, and has come into use for many applications. At the IEEE, high-speed standardization has been discussed and has seen the adoption of new technologies such as multi-level modulation formats, high baud rate modulation and dense wave length division multiplexing. The MSA transceiver form factor has also been discussed following IEEE standardization. Optical devices such as TOSA and ROSA have been required to become more compact and higher-speed, because each transceiver form factor has to be miniaturized for high-density construction. We introduce the technologies for realizing 100GbE and those applicable to 400GbE. We also discuss future packages for optical devices. There are many similarities between optical device packages and electrical device packages, and we predict that optical device packages will follow the trends seen in electrical devices. But there are also differences between optical and electrical devices. It is necessary to utilize new technology for specific optical issues to employ advanced electrical packaging and catch up the trends.

The elastic optical network (EON) is a promising new optical technology that uses spectrum resources much more efficiently than does traditional wavelength division multiplexing (WDM). This paper focuses on the routing, modulation level, spectrum and transceiver allocation (RMSTA) problems of the EON. In contrast to previous works that consider only the routing and spectrum allocation (RSA) or routing, modulation level and spectrum allocation (RMSA) problems, we additionally consider the transceiver allocation problem. Because transceivers can be used to regenerate signals (by connecting two transceivers back-to-back) along a transmission path, different regeneration sites on a transmission path result in different spectrum and transceiver usage. Thus, the RMSTA problem is both more complex and more challenging than are the RSA and RMSA problems. To address this problem, we first propose an integer linear programming (ILP) model whose objective is to optimize the balance between spectrum usage and transceiver usage by tuning a weighting coefficient to minimize the cost of network operations. Then, we propose a novel virtual network-based heuristic algorithm to solve the problem and present the results of experiments on representative network topologies. The results verify that, compared to previous works, the proposed algorithm can significantly reduce both resource consumption and time complexity.

A fully integrated CMOS pulse transceiver with digital beam-formability for mm-wave active imaging is presented. The on-chip pulse transmitter of the transceiver includes an eight-element antenna array connected to eight pulse transmitters and a built-in relative pulse delay calibration system. The receiver employs a non-coherent detection method by using a FET direct-power detection circuit integrated with an antenna. The receiver dipole-patch antenna derives from the transmitter antenna but is modified with an on-chip DC-bias tail by shorting two arms of the dipole. The bandwidth of the receiver antenna with the DC-bias tail is designed to achieve 50.4-GHz in simulation and to cover the bandwidth of transmitter antennas. The output of the receiver antenna is connected to a resistive self-mixer followed by an on-chip low pass filter and then an amplifier stage. The built-in relative pulse delay calibration system is used to align the pulse delays of each transmitter array elements for the purpose of controlling the beam steering towards imaging objects. Both transmitter and receiver chips are fabricated in a 65-nm CMOS technology process. Measured pulse waveform of the receiver after relatively aligning all Tx's pulses is 0.91 mV (peak-peak) and 3-ns duration with a distance of 25mm between Rx and Tx. Beam steering angles are achieved in measurement by changing the digital delay code of antenna elements. Experimental results show that the proposed on-chip transceiver has an ability of digital transmitted-pulse calibration, controlling of beam-steeting, and pulse detection for active imaging applications.

This letter considers the robust transceiver design for multiple-input multiple-output interference channels under channel state information mismatch. According to alternating schemes, an adaptive algorithm is proposed to solve the minimum SINR maximization problem. Simulation results show the convergence and the effectiveness of the proposed algorithm.

In order to realize an Internet-of-Things (IoT) with tiny sensors integrated in our buildings, our clothing, and the public spaces, battery lifetime and battery size remain major challenges. Power reduction in IoT sensor nodes is determined by both sleep mode as well as active mode contributions. A power state machine, at the system level, is the key to achieve ultra-low average power consumption by alternating the system between active and sleep modes efficiently. While, power consumption in the active mode remains dominant, other power contributions like for timekeeping in standby and sleep conditions are becoming important as well. For example, non-conventional critical blocks, such as crystal oscillator (XO) and resistor-capacitor oscillator (RCO) become more crucial during the design phase. Apart from power reduction, low-voltage operation will further extend the battery life. A 2.4GHz multi-standard radio is presented, as a test case, with an average power consumption in the µW range, and state-of-the-art performance across a voltage supply range from 1.2V to 0.9V.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.

In this paper, we propose two secure multiuser multiple-input multiple-output (MIMO) transmission approaches based on interference alignment (IA) in the presence of an eavesdropper. To deal with the information leakage to the eavesdropper as well as the interference signals from undesired transmitters (Txs) at desired receivers (Rxs), our approaches aim to design the transmit precoding and receive subspace matrices to minimize both the total inter-main-link interference and the wiretapped signals (WSs). The first proposed IA scheme focuses on aligning the WSs into proper subspaces while the second one imposes a new structure on the precoding matrices to force the WSs to zero. In each proposed IA scheme, the precoding matrices and the receive subspaces at the legitimate users are alternatively selected to minimize the cost function of a convex optimization problem for every iteration. We provide the feasible conditions and the proofs of convergence for both IA approaches. The simulation results indicate that our two IA approaches outperform the conventional IA algorithm in terms of the average secrecy sum rate.

In the development of intrabody communication systems, it is important to understand the effects of user's posture on the communication channels. In this study, dynamic measurements of intrabody communication channels were made and their dependences on the grounding conditions were investigated. Furthermore, the physical mechanism of the dynamic communication channels was discussed based on electrostatic simulations. According to the measured and the simulated results, the variations in the signal transmission characteristics depend not only on the distance between the Tx and the Rx but also on the shadowing by body parts.

A low-complexity time-frequency multiplex estimator and low-complexity equalizer transceiver design are proposed to combat the problems of RF impairment associated with zero-IF transceiver of multi-carrier systems. Moreover, the proposed preambles can estimate the transmitter (TX) in-phase and quadrature-phase (IQ) imbalance, carrier frequency offset (CFO), and channel impulse response parameters. The proposed system has two parts. First, all parameters of the impairments are estimated by the designed time-frequency multiplex estimator. Second, the estimated parameters are used to compensate the above problems and detect the transmitted signal with low complexity. Simulation results confirm that the proposed estimator performs reliably with respect to IQ imbalance, CFO, and multipath fading channel effects.

Wide area virtualization of wireless transceivers by centrally managed software radio systems is a way to efficiently share the resources for supporting a variety of wireless protocols. In order to enable wide-area virtualization of wireless transceivers, the authors have developed a mechanism to deliver the radio space information which is quantized broadband radio wave information including the radio signals to the transceivers. Delivery mechanism consists of a distribution server which distributes radio space corresponding to the request of the client such as the center frequency and the bandwidth and a client which uses the radio space information. Accumulation of the distribution servers which deliver radio space information simultaneously to a large number of clients will contribute to build an infrastructure for any clients ubiquitously distributed over the globe. In this paper, scale-out architecture of a distribution server is proposed to deliver unlimitedly broadband radio space information to unlimited number of clients. Experimental implementation indicates the architecture to be a scale-out solution, while the number of clients is restricted by the computer resources of the distribution server. The band pass filter processing for individual client in the distribution server consumes the dominant part of the processing power, and the number of CPU cores is the upper limit of clients supportable for the distribution server in the current operating system implementation. The logical increase of the number of CPU cores by hardware multithreading does not contribute to relax this limit. We also discuss the guidance architecture or building server derived from these conclusions.

An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.

This paper presents a novel decision feedback equalizer (DFE) with block delay detection for the joint transceiver design that uses channel state information (CSI). The block delay detection in the proposed DFE offers a degree of freedom for optimizing the precoder of the transmitter, provided the transmission power is constrained. In the proposed DFE, the feedforward matrix is devised to enable a block-based equalizer that can be cooperated with an intrablock decision feedback equalizer for suppressing the intersymbol interference (ISI) for the transmitted block with a certain block delay. In this design, the interblock interference (IBI) for the delay block is eliminated in advance by applying the recently developed oblique projection framework to the implementation of the feedforward matrix. With knowledge of full CSI, the block delay and the associated block-based precoder are jointly designed such that the average bit-error-rate (BER) is minimized, subject to the transmission power constraint. Separate algorithms are derived for directly determining the BER-minimized block delays for intrablock minimum mean-squared error (MMSE) and zero-forcing (ZF) equalization criteria. Theoretical derivations indicate that the proposed MMSE design simultaneously maximize the Gaussian mutual information of a transceiver, even under the cases of existing IBI. Simulation results validate the proposed DFE for devising an optimum transceiver with CSI, and show the superior BER performance of the optimized transceiver using proposed DFE. Relying on analytic results and simulation cases also builds a sub-optimum MMSE design of the proposed DFE using the BER-minimized block delay for ZF criterion, which exhibits almost identical BER performance as the proposed MMSE design in most of the signal-to-noise ratio (SNR) range.

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple on-off keying (OOK) modulation is adopted for low power consumption. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumption of the transmitter and receiver are 19.2 mA and 48.2 mA respectively. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.

This letter considers a dual-hop multiuser MIMO amplify-and-forward relay broadcast system with multi-antenna nodes. A unified scheme is addressed to jointly optimize the linear transceiver based on the sum mean-square error (MSE) and the sum rate criterion. The solutions are iteratively obtained by deriving the gradients of the objective functions for a gradient descent algorithm. Simulation results demonstrate the performance improvements in terms of the BER and the sum rate.

This letter proposes an algorithm of determining the BER-minimized block delay for detection and the associated precoder design once the channel state information and limited transmission power are given. Simulation cases demonstrate the adjusting capability of the proposed algorithm for achieving best BER performance of the joint linear transceiver design.