IEICE TRANSACTIONS on Fundamentals
A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
Summary :
A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E105-A No.3 pp.478-486
- Publication Date
- 2022/03/01
- Publicized
- 2021/09/03
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2021VLP0001
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Atsutake KOSUGE
The Univ. of Tokyo
Mototsugu HAMADA
The Univ. of Tokyo
Tadahiro KURODA
The Univ. of Tokyo
Keyword
Latest Issue
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Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, "A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 3, pp. 478-486, March 2022, doi: 10.1587/transfun.2021VLP0001.
Abstract: A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021VLP0001/_p
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@ARTICLE{e105-a_3_478,
author={Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System},
year={2022},
volume={E105-A},
number={3},
pages={478-486},
abstract={A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.},
keywords={},
doi={10.1587/transfun.2021VLP0001},
ISSN={1745-1337},
month={March},}
Copy
TY - JOUR
TI - A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 478
EP - 486
AU - Atsutake KOSUGE
AU - Mototsugu HAMADA
AU - Tadahiro KURODA
PY - 2022
DO - 10.1587/transfun.2021VLP0001
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2022
AB - A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
ER -
English
