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A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System

Atsutake KOSUGE, Mototsugu HAMADA, Tadahiro KURODA

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Summary :

A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E105-A No.3 pp.478-486
Publication Date
2022/03/01
Publicized
2021/09/03
Online ISSN
1745-1337
DOI
10.1587/transfun.2021VLP0001
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category

Authors

Atsutake KOSUGE
  The Univ. of Tokyo
Mototsugu HAMADA
  The Univ. of Tokyo
Tadahiro KURODA
  The Univ. of Tokyo

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