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Atsutake KOSUGE Mototsugu HAMADA Tadahiro KURODA
A 6.5Gb/s shared bus that uses a 65nm CMOS pulse transceiver chip with a low frequency equalizer and electromagnetic connectors based on two types of transmission line couplers is presented. The amount of backplane wiring is reduced by a factor of 1/16 and total connector volume by a factor of 1/246. It reduces the size and weight of a satellite processor system by 60%, increases the data rate by a factor of 2.6, and satisfies the EMC standard for withstanding the strong shock of rocket launch.
Mototsugu HAMADA Tadahiro KURODA
This paper describes transmission line couplers for non-contact connecters. Their characteristics are formulated in closed forms and design methodologies are presented. As their applications, three different types of transmission line couplers, two-fold transmission line coupler, single-ended to differential conversion transmission line coupler, and rotatable transmission line coupler are reviewed.
Tsutomu TAKEYA Tadahiro KURODA
This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.