IEICE TRANSACTIONS on Fundamentals
Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications
Summary :
This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.5 pp.940-946
- Publication Date
- 2013/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.940
- Type of Manuscript
- PAPER
- Category
- Circuit Theory
Authors
Keyword
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Tsutomu TAKEYA, Tadahiro KURODA, "Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 5, pp. 940-946, May 2013, doi: 10.1587/transfun.E96.A.940.
Abstract: This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.940/_p
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@ARTICLE{e96-a_5_940,
author={Tsutomu TAKEYA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications},
year={2013},
volume={E96-A},
number={5},
pages={940-946},
abstract={This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.},
keywords={},
doi={10.1587/transfun.E96.A.940},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - Transmission Line Coupler Design and Mixer-Based Receiver for Dicode Partial Response Communications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 940
EP - 946
AU - Tsutomu TAKEYA
AU - Tadahiro KURODA
PY - 2013
DO - 10.1587/transfun.E96.A.940
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2013
AB - This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.
ER -
English
