High-speed clock distribution design is becoming increasingly difficult and challenging task due to the huge power consumption and jitter caused by large capacitive loading and multiple repeater stages. This paper proposes a novel low-power, GHz-band bufferless LC-DCO which directly drives 10 mm on-chip clock distribution line for high-speed serial links. The shared LC-tank structure between DCO frequency tuning capacitor and clock distribution line mitigate the frequency sensitivity and makes an energy-efficient, area-saving, high-speed operation possible. The test-chip is implemented under TSMC 0.18µm, 1-poly, 6-metal CMOS technology and the core area of proposed LC-DCO is only 270×280µm2. The full-chip post layout simulation results show 2.54GHz oscillation frequency, 2.2mA current consumption and phase noise of -123dBc/Hz at 1MHz offset.

The growing demand for high-speed data communication has continued to meet the need for ever-increasing I/O bandwidth in recent VLSI systems. However, signal integrity issues, such as intersymbol interference (ISI) and reflections, make the channel band-limited at high-speed data rates. We propose high-speed data transmission techniques for VLSI systems using Tomlinson-Harashima precoding (THP). Because THP can eliminate ISI by inverting the characteristics of channels with limited peak and average power at the transmitter, it is suitable for implementing advanced low-voltage and high-speed VLSI systems. This paper presents a novel double-rate THP equalization technique especially intended for multi-valued data transmission to further improve THP performance. Simulation and measurement results show that the proposed THP equalization with a double sampling rate can enhance the data transition time and, therefore, improve the eye opening.

This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.

In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.

In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 µm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results.

This paper presents the design of new fully differential CMOS class A and class AB current-mode transmitters for multi-Gbps serial links. A high multiplexing speed is achieved by multiplexing at low-impedance nodes and inductive shunt peaking with active inductors. The fully complementary operation of the multiplexers and the fully differential configuration of the transmitters minimizes the effect of common-mode disturbances and that of EMI from channels to neighboring devices. Large output current swing is obtained by making use of differential current amplifiers and the differential rail-to-rail configuration. The constant current drawn from the supply voltage minimizes the noise injected into the substrate. The transmitters have been implemented in TSMC's 1.8 V 0.18 µm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V device models. Simulation results confirm that the proposed transmitters are capable of transmitting data at 10 Gbps.