IEICE TRANSACTIONS on Fundamentals
Symbol-Rate Clock Recovery for Integrating DFE Receivers
Summary :
In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.3 pp.705-712
- Publication Date
- 2013/03/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.705
- Type of Manuscript
- PAPER
- Category
- Communication Theory and Signals
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Keyword
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Tsutomu TAKEYA, Tadahiro KURODA, "Symbol-Rate Clock Recovery for Integrating DFE Receivers" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 3, pp. 705-712, March 2013, doi: 10.1587/transfun.E96.A.705.
Abstract: In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.705/_p
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@ARTICLE{e96-a_3_705,
author={Tsutomu TAKEYA, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Symbol-Rate Clock Recovery for Integrating DFE Receivers},
year={2013},
volume={E96-A},
number={3},
pages={705-712},
abstract={In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.},
keywords={},
doi={10.1587/transfun.E96.A.705},
ISSN={1745-1337},
month={March},}
Copy
TY - JOUR
TI - Symbol-Rate Clock Recovery for Integrating DFE Receivers
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 705
EP - 712
AU - Tsutomu TAKEYA
AU - Tadahiro KURODA
PY - 2013
DO - 10.1587/transfun.E96.A.705
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2013
AB - In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.
ER -
English
