In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.

This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.