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[Keyword] receiver architecture(2hit)

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  • WBAN Energy Efficiency and Dependability Improvement Utilizing Wake-Up Receiver Open Access

    Juha PETÄJÄJÄRVI  Heikki KARVONEN  Konstantin MIKHAYLOV  Aarno PÄRSSINEN  Matti HÄMÄLÄINEN  Jari IINATTI  

     
    INVITED PAPER

      Vol:
    E98-B No:4
      Page(s):
    535-542

    This paper discusses the perspectives of using a wake-up receiver (WUR) in wireless body area network (WBAN) applications with event-driven data transfers. First we compare energy efficiency between the WUR-based and the duty-cycled medium access control protocol -based IEEE 802.15.6 compliant WBAN. Then, we review the architectures of state-of-the-art WURs and discuss their suitability for WBANs. The presented results clearly show that the radio frequency envelope detection based architecture features the lowest power consumption at a cost of sensitivity. The other architectures are capable of providing better sensitivity, but consume more power. Finally, we propose the design modification that enables using a WUR to receive the control commands beside the wake-up signals. The presented results reveal that use of this feature does not require complex modifications of the current architectures, but enables to improve energy efficiency and latency for small data blocks transfers.

  • Symbol-Rate Clock Recovery for Integrating DFE Receivers

    Tsutomu TAKEYA  Tadahiro KURODA  

     
    PAPER-Communication Theory and Signals

      Vol:
    E96-A No:3
      Page(s):
    705-712

    In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UIPP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.