Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link
Summary :
In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 µm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.10 pp.2009-2019
- Publication Date
- 2005/10/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.10.2009
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Chih-Hsien LIN, Chang-Hsiao TSAI, Chih-Ning CHEN, Shyh-Jye JOU, "Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 10, pp. 2009-2019, October 2005, doi: 10.1093/ietele/e88-c.10.2009.
Abstract: In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 µm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.10.2009/_p
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@ARTICLE{e88-c_10_2009,
author={Chih-Hsien LIN, Chang-Hsiao TSAI, Chih-Ning CHEN, Shyh-Jye JOU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link},
year={2005},
volume={E88-C},
number={10},
pages={2009-2019},
abstract={In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 µm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results.},
keywords={},
doi={10.1093/ietele/e88-c.10.2009},
ISSN={},
month={October},}
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TY - JOUR
TI - Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link
T2 - IEICE TRANSACTIONS on Electronics
SP - 2009
EP - 2019
AU - Chih-Hsien LIN
AU - Chang-Hsiao TSAI
AU - Chih-Ning CHEN
AU - Shyh-Jye JOU
PY - 2005
DO - 10.1093/ietele/e88-c.10.2009
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2005
AB - In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 µm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results.
ER -
English
