This paper formulates minimal word-line (WL) delay time with pre-emphasis pulses to design the pulse width as a function of the overdrive voltage for large memory arrays such as 3D NAND. Circuit theory for a single RC line only with capacitance to ground and that only with coupling capacitance as well as a general case where RC lines have both grounded and coupling capacitance is discussed to provide an optimum pre-emphasis pulse width to minimize the delay time. The theory is expanded to include the cases where the resistance of the RC line driver is not negligibly small. The minimum delay time formulas of a single RC delay line and capacitive coupling RC lines was in good agreement (i.e. within 5% error) with measurement. With this research, circuit designers can estimate an optimum pre-emphasis pulse width and the delay time for an RC line in the initial design phase.

This paper presents an analysis of the relationship between noise and bandwidth in visible light communication (VLC) systems. In the past few years, pre-emphasis and post-equalization techniques were proposed to extend the bandwidth of VLC systems. However, these bandwidth extension techniques also influence noise and sensitivity of the VLC systems. In this paper, first, we build a system model of VLC transceivers and circuit models of pre-emphasis and post-equalization. Next, we theoretically compare the bandwidth and noise of three different transceiver structures comprising a single pre-emphasis circuit, a single post-equalization circuit and a combination of pre-emphasis and post-equalization circuits. Finally, we validate the presented theoretical analysis using experimental results. The result shows that for the same resonant frequency, and for high signal-to-noise ratio (S/N), VLC systems employing post-equalization or pre-emphasis have the same bandwidth extension ability. Therefore, a transceiver employing both the pre-emphasis and post-equalization techniques has a bandwidth √2 times the bandwidth of the systems employing only the pre-emphasis or post-equalization. Based on the theoretical analysis of noise, the VLC system with only active pre-emphasis shows the lowest noise, which is a good choice for low-noise systems. The result of this paper may provide a new perspective of noise and sensitivity of the bandwidth extension techniques in VLC systems.

A laser imaging detection and ranging (LIDAR) is one of the key sensors for autonomous driving. In order to improve its performance of the measurable distance, especially toward the front-side direction of the vehicle, this paper presents rapid revolution speed control of a brushless DC (BLDC) motor with a cyclostationary command signal. This enables the increase of the signal integration time for the designated direction, and thus improves the signal-to-noise ratio (SNR), while maintaining the averaged revolution speed. We propose the use of pre-emphasis circuits to accelerate and decelerate the revolution speed of the motor rapidly, by modifying the command signal so as to enhance the transition of the speed. The adaptive signal processing can adjust coefficients of the pre-emphasis filter automatically, so that it can compensate for the decayed response of the motor and its controller. Experiments with a 20-W BLDC motor prove that the proposed technique can achieve the actual revolution speed output to track the designated speed profile ranging from 600 to 1400 revolutions per minute (rpm) during one turn.

This paper describes the design and experiment results of a 25Gbps vertical-cavity surface emitting laser (VCSEL) driver circuit for a multi channel optical transmitter. To compensate for the non-linearity of the VCSEL and achieve high speed data rate communication, an asymmetric pre-emphasis technique is proposed for the VCSEL driver. An asymmetric pre-emphasis signal can be created by adjusting the duty ratio of the emphasis signal. The VCSEL driver adopts a double cascode connection that can apply a drive current from a high voltage DC bias and feed-forward compensation that can enhance the band-width for common-cathode VCSEL. For the design of the optical module structure, a two-tier low temperature co-fired ceramics (LTCC) package is adopted to minimize the wire bonding between the signal pad on the LTCC and the anode pad on the VCSEL. This structure and circuit reduces the simulated deterministic jitter from 12.7 to 4.1ps. A test chip was fabricated with the 65-nm standard CMOS process and demonstrated to work as an optical transmitter. An experimental evaluation showed that this VCSEL driver with asymmetric pre-emphasis reduced the total deterministic jitter up to 8.6ps and improved the vertical eye opening ratio by 3% compared with symmetric pre-emphasis at 25Gbps with a PRBS=29-1 test signal. The power consumption of the VCSEL driver was 3.0mW/Gbps/ch at 25Gbps. An optical transmitter including the VCSEL driver achieved 25-Gbps, 4-ch fully optical links.

A 50-Gb/s optical transmitter, consisting of a 25-Gb/s-class lens-integrated DFB-LD (with -3-dB bandwidth of 20GHz) and a LD-driver chip based on 0.18-µm SiGe BiCMOS technology for inter and intra-rack transmissions, was developed and tested. The DFB-LD and LD driver chip are flip-chip mounted on an alumina ceramic package. To suppress inter-symbol interference due to a shortage of the DFB-LD bandwidth and signal reflection between the DFB-LD and the package, the LD driver includes a two-tap pre-emphasis circuit and a high-speed termination circuit. Operating at a data rate of 50Gb/s, the optical transmitter enhances LD bandwidth and demonstrated an eye opening with jitter margin of 0.23UI. Power efficiency of the optical transmitter at a data rate of 50Gb/s is 16.2mW/Gb/s.

This paper presents a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower supply voltage. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects. Also, a new data-dependent adaptive time-domain pre-emphasis technique is proposed to compensate for the data-dependent jitter.

In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 µm 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results.