One of the most serious challenges facing the exponential performance growth in the information industry is a bandwidth bottleneck in inter-chip interconnects. We therefore propose a photonics-electronics convergence system with a silicon optical interposer. We examined integration between photonics and electronics and integration between light sources and silicon substrates, and we fabricated a conceptual model of the proposed system based on the results of those examinations. We also investigated the configurations and characteristics of optical components for the silicon optical interposer: silicon optical waveguides, silicon optical splitters, silicon optical modulators, germanium photodetectors, arrayed laser diodes, and spot-size converters. We then demonstrated the feasibility of the system by fabricating a high-density optical interposer by using silicon photonics integrated with these optical components on a single silicon substrate. As a result, we achieved error-free data transmission at 12.5 Gbps and a high bandwidth density of 6.6 Tbps/cm2 with the optical interposer. We think that this technology will solve the bandwidth bottleneck problem.

Well-defined wavelength distributed feedback laser diodes (DFB-LDs) are required in WDM network systems. Since the EDFA gain bands have been expanded, even more wavelengths are needed for large-capacity dense-WDM transmission systems. A precisely pitch-controlled Bragg grating fabricated by electron beam (EB) lithography is very attractive for realizing these DFB-LDs. This paper describes this precise pitch- and phase-controlled grating delineated by a novel method called weighted-dose allocation variable-pitch EB-lithography (WAVE). In this method, an EB-dose profile for the grating is precisely controlled by a combination of the allocation and weighting of multiple exposures. This enables us to fabricate a precise fixed-pitch grating as well as a flexible grating with a continuously chirped structure. The stitching error at the exposure field boundary, the grating pitch, and the phase shift were evaluated by using a moire pattern generated by superimposing the microscope raster scan and the grating on a wafer. We also estimated amounts of the stitching errors from fabricated and calculated lasing characteristics, and clarified that the affect of the errors on the single-mode stability of LDs is negligible. Precise wavelength controlled λ/4 phase shifted DFB-LDs were successfully demonstrated as a result of both the WAVE method and the highly uniform MOVPE crystal growth.

A 50-Gb/s optical transmitter, consisting of a 25-Gb/s-class lens-integrated DFB-LD (with -3-dB bandwidth of 20GHz) and a LD-driver chip based on 0.18-µm SiGe BiCMOS technology for inter and intra-rack transmissions, was developed and tested. The DFB-LD and LD driver chip are flip-chip mounted on an alumina ceramic package. To suppress inter-symbol interference due to a shortage of the DFB-LD bandwidth and signal reflection between the DFB-LD and the package, the LD driver includes a two-tap pre-emphasis circuit and a high-speed termination circuit. Operating at a data rate of 50Gb/s, the optical transmitter enhances LD bandwidth and demonstrated an eye opening with jitter margin of 0.23UI. Power efficiency of the optical transmitter at a data rate of 50Gb/s is 16.2mW/Gb/s.

A wide-tuning-range LC-tuned voltage-controlled oscillator (LC-VCO) – featuring small VCO-gain (KVCO) variation – has been developed. For small KVCO variation, a serial LC-resonator that consists of an inductor, a fine-tuning varactor, and a capacitor bank was added to a conventional parallel LC-resonator that uses a capacitor bank scheme. The resonator was applied to a 3.9-GHz VCO for multi-band W-CDMA RFIC fabricated using 0.25-µm Si-BiCMOS technology. The VCO exhibited KVCO variation of only 21%, which is one third that of a conventional VCO, with a 34% tuning range. The VCO also exhibited a low phase noise of -121 dBc/Hz at 1-MHz offset frequency and a low current consumption of 6.0 mA.

12-channel DC to 622-Mbit/s/ch optical transmitter and receiver have been developed for high-capacity and rather long (about 100 m) bit-parallel raw data transmission in intra- and inter-cabinet interconnection of large-scale switching, routing and computing system. Bit-parallel raw data transmission is done by using a bit-by-bit operational automatic decision threshold control receiver circuit with a DC-coupled configuration, the pin-PDs with their anodes and cathodes separated in a channel-by-channel manner, and a receiver preamplifier with a low-pass filter. The transmitter consists of a 12-channel LD sub-assembly unit and a LD driver LSI. The LD sub-assembly unit consists of a 12-channel array of high temperature characteristic 1.3-µm planar buried hetero-structure (PBH) LDs and 62.5/125 graded-index multi-mode fibers (GI62.5 MMFs). The 1.3-µm PBH LDs and the GI62.5 MMFs are optically coupled by passively visual alignment technology on the Si V-groove. The receiver consists of a 12-channel pin-PD sub-assembly unit and a receiver LSI. The pin-PD sub-assembly unit consist of a 12-channel array of pin-PDs and GI62.5 MMFs. They are optically coupled by using a flip-chip bonding on the Si V-groove. The transmitter and receiver each have eleven data channels and one clock channel. The size is as small as 3.6 cc for each modules, and the power consumptions are 1.7 W (transmitter) and 1.35 W (receiver). They transmitted a bit-parallel raw data through a 100-meter ribbon of GI62.5 MMFs in an ambient temperature range of 0-70C. They provide a synchronous PECL interface parallel link for with a 3.3-V single power supply.

Low-crosstalk 1.3-µm Fabry-Perot laser diode (FP-LD) and photodiode (PD) arrays are developed. The arrays are fabricated on semi-insulating substrates and their anodes and cathodes are separated channel by channel to suppress inter-channel electrical crosstalk at high frequency. Crosstalk of less than -30 dB is achieved between neighboring LDs at 3.125 GHz. This is low enough for BER characteristics observed under asynchronous operation of a 4-channel LD array to be no worse than those under single-channel operation. Excellent uniformity of both LD and PD characteristics, high-temperature operation of the LD array, and low-voltage operation of the PD array are also attained. These arrays are suitable for low-cost high-bit-rate parallel optical communications.

Optical I/O core based on silicon photonics technology and optical/electrical assembly was developed as a fingertip-size optical module with high bandwidth density, low power consumption, and high temperature operation. The advantages of the optical I/O core, including hybrid integration of quantum dot laser diode and optical pin, allow us to achieve 300-m transmission at 25Gbps per channel when optical I/O core is mounted around field-programmable gate array without clock data recovery.