The primary challenges faced by wireless sensor networks are how to construct the shortest spanning tree and how to determine the optimal sink node position in terms of minimizing the data transmission times and their variances for data gathering from all sensor nodes to a sink node. To solve these two problems, we propose a novel algorithm that uses the polygonal affine shortening algorithm with flow aggregation. This algorithm enables a wireless sensor network that has movable sensor nodes and one movable sink node to self-organize the shortest spanning tree and self-determine the optimal sink node position in a fully distributed manner. We also show that our algorithm is faster than the existing shortest path algorithm in terms of computational complexity.

12-channel DC to 622-Mbit/s/ch optical transmitter and receiver have been developed for high-capacity and rather long (about 100 m) bit-parallel raw data transmission in intra- and inter-cabinet interconnection of large-scale switching, routing and computing system. Bit-parallel raw data transmission is done by using a bit-by-bit operational automatic decision threshold control receiver circuit with a DC-coupled configuration, the pin-PDs with their anodes and cathodes separated in a channel-by-channel manner, and a receiver preamplifier with a low-pass filter. The transmitter consists of a 12-channel LD sub-assembly unit and a LD driver LSI. The LD sub-assembly unit consists of a 12-channel array of high temperature characteristic 1.3-µm planar buried hetero-structure (PBH) LDs and 62.5/125 graded-index multi-mode fibers (GI62.5 MMFs). The 1.3-µm PBH LDs and the GI62.5 MMFs are optically coupled by passively visual alignment technology on the Si V-groove. The receiver consists of a 12-channel pin-PD sub-assembly unit and a receiver LSI. The pin-PD sub-assembly unit consist of a 12-channel array of pin-PDs and GI62.5 MMFs. They are optically coupled by using a flip-chip bonding on the Si V-groove. The transmitter and receiver each have eleven data channels and one clock channel. The size is as small as 3.6 cc for each modules, and the power consumptions are 1.7 W (transmitter) and 1.35 W (receiver). They transmitted a bit-parallel raw data through a 100-meter ribbon of GI62.5 MMFs in an ambient temperature range of 0-70C. They provide a synchronous PECL interface parallel link for with a 3.3-V single power supply.

Optical interfaces have been recently standardized as the main physical layer interfaces for most short length optical communication systems, such as IEEE802.3ae, OIF-VSR, and the Fiber Channel. As interface speed increases, the requirements for forecasting the optical characteristics of direct modulated laser diodes (LDs) also increase because those standards define the specifications for physical layers with optical domains. In this paper, a vertical-cavity surface-emitting laser (VCSEL) equivalent electronic circuit model is described with which designers can simulate the $I-L-V$, S-parameter, and transient characteristics of LDs on a circuit simulator by improving convergence. We show that the proposed VCSEL model can model an 850-nm bandwidth VCSEL with 10-Gbps operation.