Aiming to solve the input/output (I/O) bottleneck concerning next-generation interconnections, 5×5-millimeters-squared silicon-photonics-based chip-scale optical transmitters/receivers (TXs/RXs) — called “optical I/O cores” — were developed. In addition to having a compact footprint, by employing low-power-consumption integrated circuits (ICs), as well as providing multimode-fiber (MMF) transmission in the O band and a user-friendly interface, the developed optical I/O cores allow common ease of use with applications such as multi-chip modules (MCMs) and active optical cables (AOCs). The power consumption of their hybrid-integrated ICs is 5mW/Gbps. Their high-density user-friendly optical interface has a spot-size-converter (SSC) function and permits the physical contact against the outer waveguides. As a result, they provide large enough misalignment tolerance to allow use of passive alignment and visual alignment. In a performance test, they demonstrated 25-Gbps/ch error-free operation over 300-m MMF.

This paper describes packaging techniques based on a novel passive alignment technique as key techniques for module assembly. A laser diode (LD) is passively positioned by detecting a pair of alignment marks located on the LD and Si substrate. A single-mode fiber is self aligned on a Si V groove. A simple receptacle structure for the module output port is also newly designed. This structure is more suitable for the automatic assembly line as well as the module mounting process on circuit board. In this paper, an advanced module applications such as a hybrid integrated wave guide module and a surface mountable (SMT) LD module is introduced.

Optical I/O core based on silicon photonics technology and optical/electrical assembly was developed as a fingertip-size optical module with high bandwidth density, low power consumption, and high temperature operation. The advantages of the optical I/O core, including hybrid integration of quantum dot laser diode and optical pin, allow us to achieve 300-m transmission at 25Gbps per channel when optical I/O core is mounted around field-programmable gate array without clock data recovery.