To meet the increasing demand for high-speed communication in VLSI (very large-scale integration) systems, next-generation high-speed data transmission standards (e.g., IEEE 802.3bs and PCIe 6.0) will adopt four-level pulse amplitude modulation (PAM-4) for data coding. Although PAM-4 is spectrally efficient to mitigate inter-symbol interference caused by bandwidth-limited wired channels, it is more sensitive than conventional non-return-to-zero line coding. To evaluate the received signal quality when using adaptive coefficient settings for a PAM-4 equalizer during data transmission, we propose an eye-opening monitor technique based on machine learning. The proposed technique uses a Gaussian mixture model to classify the received PAM-4 symbols. Simulation and experimental results demonstrate the feasibility of adaptive equalization for PAM-4 coding.

The data rate of VLSI interconnections has been increasing according to the demand for high-speed operation of semiconductors such as CPUs. To realize high performance VLSI systems, high-speed data communication has become an important factor. However, at high-speed data rates, it is difficult to achieve accurate communication without bit errors because of inter-symbol interference (ISI). This paper presents high-speed data communication techniques for VLSI systems using Tomlinson-Harashima Precoding (THP). Since THP can eliminate the ISI with limiting average and peak power of transmitter signaling, THP is suitable for implementing advanced low-voltage VLSI systems. In this paper, 4-PAM (Pulse amplitude modulation) with THP has been employed to achieve high-speed data communication in VLSI systems. Simulation results show that THP can remove the ISI without increasing peak and average power of a transmitter. Moreover, simulation results clarify that multiple-valued data communication is very effective to reduce implementation costs for realizing high-speed serial links.

This paper proposes new architecture LSIs based on wave-parallel computing to provide an essential solution to the interconnection problems in massively parallel processing. The basic concept is ferquency multiplexing of digital information, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary funtions in parallel with a single module. In this paper, we discuss the design of wave-parallel image processing LSI to demonstrate the feasibility of reducing the number of interconnections among modules.

This paper investigates multiple-valued code-division multiple access (MV-CDMA) techniques and circuits for intra/inter-chip communication to achieve efficient data transmission in VLSI systems. To address the problems caused by interconnection complexity, we transmit multiplexed signals inside LSI systems employing pseudo-random orthogonal m-sequences as information carriers. A new class of multiple-valued CDMA techniques for intra-chip communication is discussed to demonstrate the feasibility of eliminating co-channel interference caused by a propagation delay of signals, e.g., clock skew. This paper describes the circuit configuration and performance evaluation of MV-CDMA systems for intra-chip communication. We first explain the principle of MV-CDMA technique, and then propose a bidirectional current-mode CMOS technique to realize compact correlation circuits for CDMA. Finally, we show the Spice and MATLAB simulation results of MV-CDMA systems, which indicate the excellent capabilities of eliminating co-channel interference.

The growing demand for high-speed data communication has continued to meet the need for ever-increasing I/O bandwidth in recent VLSI systems. However, signal integrity issues, such as intersymbol interference (ISI) and reflections, make the channel band-limited at high-speed data rates. We propose high-speed data transmission techniques for VLSI systems using Tomlinson-Harashima precoding (THP). Because THP can eliminate ISI by inverting the characteristics of channels with limited peak and average power at the transmitter, it is suitable for implementing advanced low-voltage and high-speed VLSI systems. This paper presents a novel double-rate THP equalization technique especially intended for multi-valued data transmission to further improve THP performance. Simulation and measurement results show that the proposed THP equalization with a double sampling rate can enhance the data transition time and, therefore, improve the eye opening.

This paper presents a Pulse-Width Modulation (PWM) pre-emphasis technique which utilizes time-domain information processing to increase the data rate for a given bandwidth of interconnection. The PWM pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMOS technology trends toward higher switching speeds and lower supply voltage. We discuss multiple-valued data transmission based on time-domain pre-emphasis techniques in consideration of higher-order channel effects. Also, a new data-dependent adaptive time-domain pre-emphasis technique is proposed to compensate for the data-dependent jitter.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.