In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 µm CMOS technology.

This paper proposes applications of a code-division multiplexing technique to VLSI systems free from interconnection problems. We employ a pseudo-random orthogonal m-sequence carrier as a multiplexable information carrier to achieve efficient data transmission. Using orthogonal property of m-sequences, we can multiplex several computational activities into a single circuit, and execute in parallel using multiplexed data transmission with reduced interconnection. Also, randomness of m-sequences offers the high tolerance to interference (jamming), and suppression of dynamic range of signals while maintaining a sufficient signal-to-noise ratio (SNR). We demonstrate application examples of multiplex computing circuits, neural networks, and spread-spectrum image processing to show the advantages.

This paper presents a new number representation called the Signed-Weight (SW) number system, which is useful for designing configurable counter-tree architectures for digital signal processing applications. The SW number system allows the unified manipulation of positive and negative numbers in arithmetic circuits by adjusting the signs assigned to individual digit positions. This makes possible the construction of highly regular arithmetic circuits without introducing irregular arithmetic operations, such as negation and sign extension in the two's complement representation. This paper also presents the design of a Field-Programmable Digital Filter (FPDF) architecture--a special-purpose FPGA architecture for high-speed FIR filtering--using the proposed SW arithmetic system.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

This letter proposes evolutionary digital filters (EDFs) as new adaptive digital filters. The EDF is an adaptive filter which is controlled by adaptive algorithm based on the evolutionary strategies of living things. It consists of many linear/time-variant inner digital filters which correspond to individuals. The adaptive algorithm of the EDF controls and changes the coefficients of inner filters using the cloning method (the asexual reproduction method) or the mating method (the sexual reproduction method). Thus, the search algorithm of the EDF is a non-gradient and multi-point search algorithm. Numerical examples are given to show the effectiveness and features of the EDF such that they are not susceptible to local minimum in the multiple-peak performance surface.

This letter presents an efficient design method of multiplierless 2-D state-space digital filters (SSDFs) based on a genetic algorithm. The resultant multiplierless 2-D SSDFs, whose coefficients are represented as the sum of two powers-of-two terms, are attractive for high-speed operation and simple implementation. The design problem of multiplierless 2-D SSDFs described by Roesser's local state-space model is formulated subject to the constraint that the resultant filters are stable. To ensure the stability for the resultant 2-D SSDFs, a stability test routine is embedded in th design procedure.

Roundoff error due to iterative computation with finite wordlength degrades the quality of decoded images in fractal image coding that employs a deterministic iterated function system. This paper presents a state-space approach to roundoff error analysis of fractal image coding for grey-scale images. The output noise variance matrix and the noise matrix are derived for the measures of error and the output noise variance is newly defined as the pixel mean of diagonal elements of the output noise matrix. A quantitative comparison of experimental roundoff error with analytical result is made for the output noise variance. The result shows that our analysis method is valid for the fractal image coding. Our analysis method is useful to design a real-time and low-cost decoding hardware with finite wordlength for fractal image coding.

This paper proposes an analysis method of scaling-factor-quantization error in fractal image coding using a state-space approach with the statistical analysis method. It is shown that the statistical analysis method is appropriate and leads to a simple result, whereas the deterministic analysis method is not appropriate and leads to a complex result for the analysis of fractal image coding. We derive the output error variance matrix for the measure of error and define the output error variance by scalar quantity as the mean of diagonal elements of the output error variance matrix. Examples are given to show that the scaling-factor-quantization error due to iterative computation with finite-wordlength scaling factors degrades the quality of decoded images. A quantitative comparison of experimental scaling-factor-quantization error with analytical result is made for the output error variance. The result shows that our analysis method is valid for the fractal image coding.

This paper presents a special-purpose LSI chip for inverse kinematics computation of robot manipulators. It is shown that inverse kinematic solutions of kinematically simple manipulators can be systematically described with the two-dimensional (2-D) vector rotation. The chip is fabricated with the 1.5-µm CMOS gate array. The arithmetic unit on the chip is designed using the COordinate Rotation DIgital Computer (CORDIC) algorithms, and it performs six types of operations based on the 2-D vector rotation at high speed. Pipelining is used to enhance the operating ratio of the unit to 100%. The computation time of a special purpose processor which is composed of the chip and a few memory chips is approximately 50 µs for a typical six degree-of-freedom manipulator. Moreover, the chip can be used for various types of manipulators, and the software development is very easy.

This paper presents a high-accuracy image registration technique using a Phase-Only Correlation (POC) function. Conventional techniques of phase-based image registration employ heuristic methods in estimating the location of the correlation peak, which corresponds to image displacement. This paper proposes a technique to improve registration performance by fitting the closed-form analytical model of the correlation peak to actual two-dimensional numerical data. This method can also be extended to a spectrum weighting POC technique, where we modify cross-phase spectrum with some weighting functions to enhance registration accuracy. The proposed method makes possible to estimate image displacements with 1/100-pixel accuracy.

This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

This paper proposes an efficient fingerprint recognition algorithm combining phase-based image matching and feature-based matching. In our previous work, we have already proposed an efficient fingerprint recognition algorithm using Phase-Only Correlation (POC), and developed commercial fingerprint verification units for access control applications. The use of Fourier phase information of fingerprint images makes it possible to achieve robust recognition for weakly impressed, low-quality fingerprint images. This paper presents an idea of improving the performance of POC-based fingerprint matching by combining it with feature-based matching, where feature-based matching is introduced in order to improve recognition efficiency for images with nonlinear distortion. Experimental evaluation using two different types of fingerprint image databases demonstrates efficient recognition performance of the combination of the POC-based algorithm and the feature-based algorithm.

This paper presents a high-density multiple-valued content-addressable memory (MVCAM) based on a floating-gate MOS device. In the proposed CAM, a basic operation performed in each cell is a threshold function that is a kind of inverter whose threshold value is programmable. Various multiple-valued operations for data retrieval can be easily performed using threshold functions. Moreover, each cell circuit in the MVCAM can be implemented using only a single floating-gate MOS transistor. As a result, the cell area of the four-valued CAM are reduced to 37% in comparison with that of the conventional dynamic CAM cell.

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.

This paper presents a design of a new high-density multiple-valued associative memory with incomplete information proessing capability. The degree of similarity between an input data and each memory data is evaluated by several discrete values (called multi-level matching), so that any incomplete input data can be recognized surely as a certain memory data in the associateve memory. The multiple-valued associative processing can be performmed systematically by the superposition of a new multiple-valued logic function, called multi-level matching function. The multiple-valued data is directly performmed using floatin-gate MOS device whose threshold voltage is programmable, so that the multi-level matching function can be simply implemented. It is demonstrated that the chip area and the processing time of an 8-level matching function circuit can be reduced to 3.2 % and 25 %, respectively in comparison with the corresponding binary implementation using 2-µm CMOS process.

This paper presents a shortest path search algorithm using a model of excitable reaction-diffusion dynamics. In our previous work, we have proposed a framework of Digital Reaction-Diffusion System (DRDS)--a model of a discrete-time discrete-space reaction-diffusion system useful for nonlinear signal processing tasks. In this paper, we design a special DRDS, called an "excitable DRDS," which emulates excitable reaction-diffusion dynamics and produces traveling waves. We also demonstrate an application of the excitable DRDS to the shortest path search problem defined on two-dimensional (2-D) space with arbitrary boundary conditions.

This paper presents a formal design of arithmetic circuits using an arithmetic description language called ARITH. The key idea in ARITH is to describe arithmetic algorithms directly with high-level mathematical objects (i.e., number representation systems and arithmetic operations/formulae). Using ARITH, we can provide formal description of arithmetic algorithms including those using unconventional number systems. In addition, the described arithmetic algorithms can be formally verified by equivalence checking with formula manipulations. The verified ARITH descriptions are easily translated into the equivalent HDL descriptions. In this paper, we also present an application of ARITH to an arithmetic module generator, which supports a variety of hardware algorithms for 2-operand adders, multi-operand adders, multipliers, constant-coefficient multipliers and multiply accumulators. The language processing system of ARITH incorporated in the generator verifies the correctness of ARITH descriptions in a formal method. As a result, we can obtain highly-reliable arithmetic modules whose functions are completely verified at the algorithm level.

An experimental model of a redox microarray, which provides a foundation for constructing future massively parallel molecular computers, is proposed. The operation of a redox microarray is confirmed, using an experimental setup based on an array of microelectrodes with analog integrated circuits.

This paper presents a new high-speed three-dimensional (3-D) object recognition system based on two-dimensional (2-D) chain code matching. An observed 3-D object is precisely represented by a 2-D chain code sequence from the discrete surface points of the 3-D object, so that any complex objects can be recognized precisely. Moreover, the normalization procedures such as translation, rotation of 3-D objects except scale changes can be performed systematically and regularly regardless of the complexity of the shape of 3-D objects, because almost all the normalization procedures of 3-D objects are included in the 2-D chain code matching procedure. As a result, the additional normalization procedure become only the processing time for scale changes which can be performed easily by normalizing the length of the chain code sequence. In addition, the fast fourier transformation (FFT) is applicable to 2-D chain code matching which calculates cross correlation between an input object and a reference model, so that very fast recognition is performed. In fact, it is demonstrated that the total recognition time of a 3-D ofject is estimated at 5.35 (sec) using the 28.5-MIPS SPARC workstation.

This paper proposes a new residue number multiplication scheme based on the cylic type of relationship which exists between the entries in the residue number multiplication truth-table when the modulus is any prime number. Using the scheme, multiplication is direct without table consultation and an entire truth-table is realizable. The multiplier circuit is simple and compact and allows pipelined processing of data. The flexibility of the multiplier is exploited in the implementation of an RNS based high-order FIR digital filter by using a programmable low order section. The suitability of the modular digital processor for VLSI is also indicated.