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[Author] Yoshifumi SASAKI(2hit)

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  • High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation

    Kenji TAKITA  Takafumi AOKI  Yoshifumi SASAKI  Tatsuo HIGUCHI  Koji KOBAYASHI  

     
    PAPER

      Vol:
    E86-A No:8
      Page(s):
    1925-1934

    This paper presents a high-accuracy image registration technique using a Phase-Only Correlation (POC) function. Conventional techniques of phase-based image registration employ heuristic methods in estimating the location of the correlation peak, which corresponds to image displacement. This paper proposes a technique to improve registration performance by fitting the closed-form analytical model of the correlation peak to actual two-dimensional numerical data. This method can also be extended to a spectrum weighting POC technique, where we modify cross-phase spectrum with some weighting functions to enhance registration accuracy. The proposed method makes possible to estimate image displacements with 1/100-pixel accuracy.

  • A VLSI-Oriented Model-Based Robot Vision Processor for 3-D Instrumentation and Object Recognition

    Yoshifumi SASAKI  Michitaka KAMEYAMA  

     
    PAPER

      Vol:
    E77-C No:7
      Page(s):
    1116-1122

    In robot vision system, enormously large computation power is required to perform three-dimensional (3-D) instrumentation and object recognition. However, many kinds of complex and irregular operations are required to make accurate 3-D instrumentation and object recognition in the conventional method for software implementation. In this paper, a VLSI-oriented Model-Based Robot Vision (MBRV) processor is proposed for high-speed and accurate 3-D instrumentation and object recognition. An input image is compared with two-dimensional (2-D) silhouette images which are generated from the 3-D object models by means of perspective projection. Because the MBRV algorithm always gives the candidates for the accurate 3-D instrumentation and object recognition result with simple and regular procedures, it is suitable for the implementation of the VLSI processor. Highly parallel architecture is employed in the VLSI processor to reduce the latency between the image acquisition and the output generation of the 3-D instrumentation and object recognition results. As a result, 3-D instrumentation and object recognition can be performed 10000 times faster than a 28.5 MIPS workstation.