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Takahiro HANYU Hiroto ISHII Tatsuo HIGUCHI
This paper presents a design of a new high-density multiple-valued associative memory with incomplete information proessing capability. The degree of similarity between an input data and each memory data is evaluated by several discrete values (called multi-level matching), so that any incomplete input data can be recognized surely as a certain memory data in the associateve memory. The multiple-valued associative processing can be performmed systematically by the superposition of a new multiple-valued logic function, called multi-level matching function. The multiple-valued data is directly performmed using floatin-gate MOS device whose threshold voltage is programmable, so that the multi-level matching function can be simply implemented. It is demonstrated that the chip area and the processing time of an 8-level matching function circuit can be reduced to 3.2 % and 25 %, respectively in comparison with the corresponding binary implementation using 2-µm CMOS process.