A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing

Takahiro HANYU; Hiroto ISHII; Tatsuo HIGUCHI

A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing

Takahiro HANYU, Hiroto ISHII, Tatsuo HIGUCHI

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This paper presents a design of a new high-density multiple-valued associative memory with incomplete information proessing capability. The degree of similarity between an input data and each memory data is evaluated by several discrete values (called multi-level matching), so that any incomplete input data can be recognized surely as a certain memory data in the associateve memory. The multiple-valued associative processing can be performmed systematically by the superposition of a new multiple-valued logic function, called multi-level matching function. The multiple-valued data is directly performmed using floatin-gate MOS device whose threshold voltage is programmable, so that the multi-level matching function can be simply implemented. It is demonstrated that the chip area and the processing time of an 8-level matching function circuit can be reduced to 3.2 % and 25 %, respectively in comparison with the corresponding binary implementation using 2-µm CMOS process.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.4 pp.918-928

Publication Date: 1991/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)

Category: ASIC

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Takahiro HANYU
Hiroto ISHII
Tatsuo HIGUCHI

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Takahiro HANYU, Hiroto ISHII, Tatsuo HIGUCHI, "A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 4, pp. 918-928, April 1991, doi: .
Abstract: This paper presents a design of a new high-density multiple-valued associative memory with incomplete information proessing capability. The degree of similarity between an input data and each memory data is evaluated by several discrete values (called multi-level matching), so that any incomplete input data can be recognized surely as a certain memory data in the associateve memory. The multiple-valued associative processing can be performmed systematically by the superposition of a new multiple-valued logic function, called multi-level matching function. The multiple-valued data is directly performmed using floatin-gate MOS device whose threshold voltage is programmable, so that the multi-level matching function can be simply implemented. It is demonstrated that the chip area and the processing time of an 8-level matching function circuit can be reduced to 3.2 % and 25 %, respectively in comparison with the corresponding binary implementation using 2-µm CMOS process.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_4_918/_p

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@ARTICLE{e74-c_4_918,
author={Takahiro HANYU, Hiroto ISHII, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing},
year={1991},
volume={E74-C},
number={4},
pages={918-928},
abstract={This paper presents a design of a new high-density multiple-valued associative memory with incomplete information proessing capability. The degree of similarity between an input data and each memory data is evaluated by several discrete values (called multi-level matching), so that any incomplete input data can be recognized surely as a certain memory data in the associateve memory. The multiple-valued associative processing can be performmed systematically by the superposition of a new multiple-valued logic function, called multi-level matching function. The multiple-valued data is directly performmed using floatin-gate MOS device whose threshold voltage is programmable, so that the multi-level matching function can be simply implemented. It is demonstrated that the chip area and the processing time of an 8-level matching function circuit can be reduced to 3.2 % and 25 %, respectively in comparison with the corresponding binary implementation using 2-µm CMOS process.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A Design of a High-Density Multi-Level Matching Array Chip for Associative Processing
T2 - IEICE TRANSACTIONS on Electronics
SP - 918
EP - 928
AU - Takahiro HANYU
AU - Hiroto ISHII
AU - Tatsuo HIGUCHI
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1991
AB - This paper presents a design of a new high-density multiple-valued associative memory with incomplete information proessing capability. The degree of similarity between an input data and each memory data is evaluated by several discrete values (called multi-level matching), so that any incomplete input data can be recognized surely as a certain memory data in the associateve memory. The multiple-valued associative processing can be performmed systematically by the superposition of a new multiple-valued logic function, called multi-level matching function. The multiple-valued data is directly performmed using floatin-gate MOS device whose threshold voltage is programmable, so that the multi-level matching function can be simply implemented. It is demonstrated that the chip area and the processing time of an 8-level matching function circuit can be reduced to 3.2 % and 25 %, respectively in comparison with the corresponding binary implementation using 2-µm CMOS process.
ER -