State-of-the-art dynamic random access memory (DRAM) technologies are reviewed, focusing on circuit design issues. In addition to density increase, clear trends indicated in recent reports are: (1) low-voltage and low-power DRAMs, e.g. a 1.5-3.6 V 64-Mb DRAM and a 4-Mb DRAM with a 3-µA retention current. Lowering the operating voltage is essential in termss of the reliability of miniaturized devices and the power dissipation of the chip. Besides, the resultant low operating current and the low retention current are keys to meeting the increasing demand for battery-backed or battery-operated DRAMs. Important technologies are high-speed sensing, a high-speed low-power internal voltage generator, a word-line booster, and a refresh timer; (2) High-speed DRAMs with half the access times of standard ones, e.g. 17-ns 4-Mb DRAMs. Many efforts have been made to enhance random and serial access rates, such as direct sensing and on-chip interleaving techniques. In addition to high-speed operation, the movement towards larger bit width requires a means of suppressing the noise increased due to a larger peak current. Waveform control for date-line and output charging current is essential; (3) Yield improvement and test cost reduction techniques, e.g. on-chip ECC, parallel testing, and built-in self-testing. These are becoming more and more important for reducing cost.

Leakage current in SCC DRAM was reduced by optimizing implant conditions to form channel stopper, node connection and Hi-C boron. To reduce leakage current, the implantation doses should be reduced to reduce implant induced damages. These implant dose reductions are compromised to the necessities of high p type concentration to prevent punch-throughs at several parts of the cell. Near the deep trench bottom, damaged region due to Hi-C boron implant is separated from the bottom edge of the n⁺ storage node to suppress the gate controlled leakage current. By the improvements, the retention time of the 16 M SCC DRAM becomes over 30 sec at room temperature. It is also shown that folded bit line structure could be adopted easily for SCC.

This paper describes a key technology of a small sized stacked capacitor cell to realize 16 MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, which provides reliable contacts with high immunity against process fluctuations such as overetching side-etching and pattern misalignment in photolithography. The cell made by this technology showed desirable characteristics for DRAM operation.

This paper reviews the progresses of static random access memories (SRAMs) for the last past 10 years and shows how much memory cell sizes have been reduced and how the chip sizes have increased to increase memory capacities. After a basic SRAM chip organization is briefly described for readers' convenience, various latest and important key technologies for CMOS, bipolar transistor and BiCMOS SRAMs are reviewed. Chip organizations and circuit technologies to improve performance, which have been used in recently reported high performance SRAMs, are also introduced. Future large scale and high speed SRAMs are also forecasted.

This paper describes a collected charge enhancement due to the alpha-particle-induced charge transfer through an extremely thin (less than 0.2µm) p-layer sandwiched between two n-layers. This charge enhancement is caused by a parasitic transistor composed of the p- and the two n-layers which is turned on by the alpha-particle-induced charge. The collected charge enhancement occurs depending on the impurity concentration and the thickness of the thin layer. The condition whether the charge enhancement occurs or not is determined quantitatively using a 3-D device simulator. The simulation and experimental results show that, if the collected charge enhancement occurs, the soft-error rate is dominantly determined by it and cannot be decreased by increasing the cell stored charge.

A novel logic functional level converter (FLC) was developed to achieve a high speed ECL I/O BiCMOS SRAM. The FLC simultaneously enables high speed logic operation and ECL to CMOS level conversion. This paper describes an optimized design method for the FLC and an improved FLC. In addition, a high speed partial decoding level converter (PDLC), composed of improved FLCs, is presented. The FLC and a newly developed address decoding sheme with PDLCs, are keys to the successful production of the 5ns 1Mb ECL I/O BiCMOS SRAM.

A new soft-error phenomenon in which the soft-error rate (SER) decreases as cycle time becomes shorter has been found in static RAM's (SRAM's) employing a high-resistive load memory cell. This inverted dependence is observed during the read cycle in the SRAM's involving the PMOS bit-line load. The SER at the cycle time of 100 ns is reduced by 1.5-orders of magnitude compared with that of conventional SRAM's. The convertional dependence of SER on cycle time has been explained with the time constant to charge up the "High" storage node potential through the high-resistive load. The mechanism of the inverted dependence becomes clear in consideration of the time constant of the potential drop of the "High" storage node. The analysis is applied to explain that three kinds of dependence of SER on cycle time, which are the conventional dependence, the inverted dependence, and no dependence, will be observed when the following cell parameters are changed. One is the threshold voltage of driver transistors in the cell, and the other is the impedance of the high-resistive load.

We report the results of experiments on a Josephson RAM having an access time of 590 ps and a power dissipation of 19 mW. To design such high-speed memory, we developed new gates and circuits and used high-speed techniques. This paper details the design of the 4K bit Josephson RAM.

Recent technical trends of electrically programmable ROM (E-PROM) and electrically erasable and programmable PROM (EE-PROM) are reviewed in this paper. The reduction of the cell size and high speed access have been realized by the several breakthroughs of the device structure. The invention of the Flash EE-PROM makes the cell size same as that of E-PROM. Therefore, the bit capacity of Flash EE-PROM is supposed to be quadrupled every three years, same as DRAM's and E-PROM's scaling speed. Furthermore, the much higher density EE-PROM can be realized by the use of the NAND EE-PROM, recently. The invention of the NAND EE-PROM has enabled the semiconductor device engineers to replace the magnetic memory with Si device in very near future.

The optimal tunnel oxide thickness in MNOS memory devices is determined for the first time to be 1.8 nm0.1 nm, by considering ten-year data retention after 10⁵ erase/write cycles at a temperature of 85. It is also demonstrated that the tunnel oxide thickness can remain constant, regardless of the extent of scaling down of MNOS memory devices, as long as the programming time is kept constant at 10 ms. In addition, we derive the programming electric field to be 4.2-5.1 MV/cm in the silicon nitride for MNOS design. As a result, a new authentic MNOS design concept is presented.

Most of the late generation nonvolatile memories with moderate access speed are designed with divided memory matrix NOR type cell structure because word and bit-lines carry a uniform array of parasitic capacitance which delays the signal propagation and causes the slow down of data access time. Even though divided memory matrix has short matrix drive a chip size penalty is large. Data read function of conventional ROM devices is performed by applying V_SS voltage at source of each memory cell MOS transistor. Selected memory cells are applied with a predetermined high-detecting bias (HDB) at the drain through selected bit-line. The current detector connected to these bit-lines detectes the level of current to maintain the bias against cell current. New low detecting bias (LDB) technology improves the data access time from wide memory cell matrix area that must be driven by long-word lines (row) and long bit-lines (column). By implementing the (LDB) ROM architecture, voltage transient time of a word line, transition period of voltage against parasitic capacitance and detection period of bit-line voltage deviation can be improved significantly.

Recently, in response to the ever increasing speed of microprocessors, high speed operation has become an important requirement for mask ROM. This paper describes the circuit technologies used in a high speed mask ROM with a 26 ns access time. The short access time was realized using new circuit techniques combined with 1.0 µm CMOS technology. A new word line drive architecture realizes a short word line rise time despite a cell pitch which is smaller than the second Al pitch. To shorten the sensing time, a fully differential sensing circuit which enables reduced boron dose transistors to be used was adopted. A low noise output buffer is also used for achieving high speed operation while reducing the peak current noise.

An 85 ns 16 Mb CMOS EPROM has been realized. It can be hard-ware configured as either 1 M 16 bits or 2 M 8 bits by controlling an input signal. An unique redundancy circuit, which includes two types of PROM cell fuses, allow testing the device completely before assembly. Bit-line division and tungsten polycide wordline are keys to achieve an 85 ns access time. A scaled EPROM cell of 3.6µm is realized with a 0.6 µm N-well CMOS technology with trench-self-aligned isolation and oxide-nitride-oxide interpoly dielectrics. The chip size is 7.1 17.1 mm.

With the great leaps forward in standard memories like DRAMs and SRAMs, demands for a dedicated memory oriented to special applications have become increasingly strong. This paper presents the state of the art of ASIC memories, explaining the key points needed to implement additional features. Trends are outlined and technological issues concerning device choice, circuit technique, and design methodology are discussed. Through consideration of future trends in ASIC memories, it's clarified that achieving high-speed performance as well as high memory capacity with sophisticated logic fills most of the special applications.

A 4096-channel time-switch LSI with switching address protection is described. To achieve the large switching capacity, a double buffer architecture was adopted, and divided cell array structures were implemented using an automatic layout method. A 4096 w 1 b protection memory is included in the control memory to avoid snappings of paths through fixed switching addresses. The memory area and design complexity were reduced by developing a new method for constructing a memory array with variable capacities and multiple-WE (Write-Enable Signal) control systems. The chip was fabricated with 0.8 µm BiCMOS technology and operates at over 32 Mb/s with a power consumption of 1.2 W.

This paper presents a design of a new high-density multiple-valued associative memory with incomplete information proessing capability. The degree of similarity between an input data and each memory data is evaluated by several discrete values (called multi-level matching), so that any incomplete input data can be recognized surely as a certain memory data in the associateve memory. The multiple-valued associative processing can be performmed systematically by the superposition of a new multiple-valued logic function, called multi-level matching function. The multiple-valued data is directly performmed using floatin-gate MOS device whose threshold voltage is programmable, so that the multi-level matching function can be simply implemented. It is demonstrated that the chip area and the processing time of an 8-level matching function circuit can be reduced to 3.2 % and 25 %, respectively in comparison with the corresponding binary implementation using 2-µm CMOS process.

A 369Kbit SRAM configurable up to four ports, namely, a Port-Configurable (PC) SRAM embedded in 235 KG track-free gate array has been newly developed. The chip fabricated with 0.5 µm double polysilicon and aluminum process technology showed 5 ns on-chip access time. This is considered to be one of the solutions for many applications that require memory system of high speed, large density and high flexibility in configuration such as number of ports, words and bits. The basic PC SRAM cell is a polysilicon resistor load SRAM cell with port customization terminals which are connected by standard gate array customization layers, first and second Al and via hole. In order that a high flexibility in column partitioning is available, a column-sliceable design is employed. Two column-sliceable sense amplifier, Trip Point Controlled CMOS (TPCC) sence amp and Symmetric Current Mirror (SCM) sense amp, are proposed to be laid out wihtin a single column pitch. One basic PC SRAM building block of 123 Kbit consists of 4 sets of decoders, 512 rows each, and 240 columns. For low power and high speed operation, double word line structure with section driving 40 columns are employed. Therefore, in addition to the port configurability, a high flexibility in row and column is available. The maximum word depth is 6 k words with 60 column single port memory. The maximum number of independently operating memory is twelve in case of single port. The chip contains three blocks of 369 kbit so that wide range of selection of cache, TLB and resistor files are integrated with MPU and other logic circuits.

This paper describes the Hierarchical Module Generation Technique capable of creating a high performance memory macrocell. The technique features: (a) automatic generation of macrocells with multi-level hierarchies that achieves the same performance as manually designed macrocells; (b) flexible configuration of macrocells in terms of word-length, bit-width, and cell-shape; and (c) equivalent logic description is created simultaneously with generated patterns that can be used for logic or delay simulation is ASIC design. Several kinds of memory macrocells have been developed as a library including a 1-port RAM, a 2-port RAM, and a ROM using 0.8-µm CMOS technology to verify the effectiveness of this technique.

In this paper, we present a study on the activity of second harmonic generation (SHG) from mixtures of organic nonlinear materials 2-methyl-4-nitroaniline (MNA) and paranitroaniline (pNA), changing the mixing ratio over a wide range. The mixtures show a maximum SHG powder efficiency of 520 ( urea) at a mixing weight ratio of MNA/pNA=40. We also present a setup for the measurement of the powder efficiency that an integrating sphere and a small hemispherical mirror are in contact with the sample cell on the reflecting and transmitting sides, respectively. This setup is conveniently used to effectively collect the second harmonic waves radiated from organic powder samples, since the transmissivity is usually very small due to scattering. The X-ray diffraction patterns indicate that the enhanced SHG activity of the mixtures may be due to some changes of MNA molecules in the direction of the hydrogen bond, though the crystal structure is unchanged. The SHG activity of the mixtures is found to be thermostable and also not to change so much for over two months.

A high speed, large capacity optical disk for commercial applications is developed. This disk system adopts both the pit-edge recording method and the MCAV method. New techniques, which can use these methods together and are suitable for interchangeability, are developed: Independent detection of leading/trailing edge and data composition. Consequently, the most reliable file system to date has been achieved.