Most of the late generation nonvolatile memories with moderate access speed are designed with divided memory matrix NOR type cell structure because word and bit-lines carry a uniform array of parasitic capacitance which delays the signal propagation and causes the slow down of data access time. Even though divided memory matrix has short matrix drive a chip size penalty is large. Data read function of conventional ROM devices is performed by applying VSS voltage at source of each memory cell MOS transistor. Selected memory cells are applied with a predetermined high-detecting bias (HDB) at the drain through selected bit-line. The current detector connected to these bit-lines detectes the level of current to maintain the bias against cell current. New low detecting bias (LDB) technology improves the data access time from wide memory cell matrix area that must be driven by long-word lines (row) and long bit-lines (column). By implementing the (LDB) ROM architecture, voltage transient time of a word line, transition period of voltage against parasitic capacitance and detection period of bit-line voltage deviation can be improved significantly.