Low Detecting Bias and Its Influence on Non-volatile Memory Data Access

Shoji KITAZAWA; Teruhiro HARADA

Low Detecting Bias and Its Influence on Non-volatile Memory Data Access

Shoji KITAZAWA, Teruhiro HARADA

Full Text Views

0

Cite this

Summary :

Most of the late generation nonvolatile memories with moderate access speed are designed with divided memory matrix NOR type cell structure because word and bit-lines carry a uniform array of parasitic capacitance which delays the signal propagation and causes the slow down of data access time. Even though divided memory matrix has short matrix drive a chip size penalty is large. Data read function of conventional ROM devices is performed by applying V_SS voltage at source of each memory cell MOS transistor. Selected memory cells are applied with a predetermined high-detecting bias (HDB) at the drain through selected bit-line. The current detector connected to these bit-lines detectes the level of current to maintain the bias against cell current. New low detecting bias (LDB) technology improves the data access time from wide memory cell matrix area that must be driven by long-word lines (row) and long bit-lines (column). By implementing the (LDB) ROM architecture, voltage transient time of a word line, transition period of voltage against parasitic capacitance and detection period of bit-line voltage deviation can be improved significantly.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.4 pp.885-889

Publication Date: 1991/04/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories)

Category: ROM

Authors

Shoji KITAZAWA
Teruhiro HARADA

Keyword

Cite this

Copy

Shoji KITAZAWA, Teruhiro HARADA, "Low Detecting Bias and Its Influence on Non-volatile Memory Data Access" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 4, pp. 885-889, April 1991, doi: .
Abstract: Most of the late generation nonvolatile memories with moderate access speed are designed with divided memory matrix NOR type cell structure because word and bit-lines carry a uniform array of parasitic capacitance which delays the signal propagation and causes the slow down of data access time. Even though divided memory matrix has short matrix drive a chip size penalty is large. Data read function of conventional ROM devices is performed by applying V_SS voltage at source of each memory cell MOS transistor. Selected memory cells are applied with a predetermined high-detecting bias (HDB) at the drain through selected bit-line. The current detector connected to these bit-lines detectes the level of current to maintain the bias against cell current. New low detecting bias (LDB) technology improves the data access time from wide memory cell matrix area that must be driven by long-word lines (row) and long bit-lines (column). By implementing the (LDB) ROM architecture, voltage transient time of a word line, transition period of voltage against parasitic capacitance and detection period of bit-line voltage deviation can be improved significantly.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_4_885/_p

Copy

@ARTICLE{e74-c_4_885,
author={Shoji KITAZAWA, Teruhiro HARADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Detecting Bias and Its Influence on Non-volatile Memory Data Access},
year={1991},
volume={E74-C},
number={4},
pages={885-889},
abstract={Most of the late generation nonvolatile memories with moderate access speed are designed with divided memory matrix NOR type cell structure because word and bit-lines carry a uniform array of parasitic capacitance which delays the signal propagation and causes the slow down of data access time. Even though divided memory matrix has short matrix drive a chip size penalty is large. Data read function of conventional ROM devices is performed by applying V_SS voltage at source of each memory cell MOS transistor. Selected memory cells are applied with a predetermined high-detecting bias (HDB) at the drain through selected bit-line. The current detector connected to these bit-lines detectes the level of current to maintain the bias against cell current. New low detecting bias (LDB) technology improves the data access time from wide memory cell matrix area that must be driven by long-word lines (row) and long bit-lines (column). By implementing the (LDB) ROM architecture, voltage transient time of a word line, transition period of voltage against parasitic capacitance and detection period of bit-line voltage deviation can be improved significantly.},
keywords={},
doi={},
ISSN={},
month={April},}

Copy

TY - JOUR
TI - Low Detecting Bias and Its Influence on Non-volatile Memory Data Access
T2 - IEICE TRANSACTIONS on Electronics
SP - 885
EP - 889
AU - Shoji KITAZAWA
AU - Teruhiro HARADA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1991
AB - Most of the late generation nonvolatile memories with moderate access speed are designed with divided memory matrix NOR type cell structure because word and bit-lines carry a uniform array of parasitic capacitance which delays the signal propagation and causes the slow down of data access time. Even though divided memory matrix has short matrix drive a chip size penalty is large. Data read function of conventional ROM devices is performed by applying V_SS voltage at source of each memory cell MOS transistor. Selected memory cells are applied with a predetermined high-detecting bias (HDB) at the drain through selected bit-line. The current detector connected to these bit-lines detectes the level of current to maintain the bias against cell current. New low detecting bias (LDB) technology improves the data access time from wide memory cell matrix area that must be driven by long-word lines (row) and long bit-lines (column). By implementing the (LDB) ROM architecture, voltage transient time of a word line, transition period of voltage against parasitic capacitance and detection period of bit-line voltage deviation can be improved significantly.
ER -