Recently, in response to the ever increasing speed of microprocessors, high speed operation has become an important requirement for mask ROM. This paper describes the circuit technologies used in a high speed mask ROM with a 26 ns access time. The short access time was realized using new circuit techniques combined with 1.0 µm CMOS technology. A new word line drive architecture realizes a short word line rise time despite a cell pitch which is smaller than the second Al pitch. To shorten the sensing time, a fully differential sensing circuit which enables reduced boron dose transistors to be used was adopted. A low noise output buffer is also used for achieving high speed operation while reducing the peak current noise.