A 26 ns 1 Mbit CMOS Mask ROM
Summary :
Recently, in response to the ever increasing speed of microprocessors, high speed operation has become an important requirement for mask ROM. This paper describes the circuit technologies used in a high speed mask ROM with a 26 ns access time. The short access time was realized using new circuit techniques combined with 1.0 µm CMOS technology. A new word line drive architecture realizes a short word line rise time despite a cell pitch which is smaller than the second Al pitch. To shorten the sensing time, a fully differential sensing circuit which enables reduced boron dose transistors to be used was adopted. A low noise output buffer is also used for achieving high speed operation while reducing the peak current noise.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E74-C No.4 pp.890-895
- Publication Date
- 1991/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
- ROM
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Keyword
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Yasuhiro HOTTA, Mikiro OKADA, Ryusuke MATSUYAMA, Hiroshi TSUGITA, Kenji SANO, Akihiko KUNIKANE, "A 26 ns 1 Mbit CMOS Mask ROM" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 4, pp. 890-895, April 1991, doi: .
Abstract: Recently, in response to the ever increasing speed of microprocessors, high speed operation has become an important requirement for mask ROM. This paper describes the circuit technologies used in a high speed mask ROM with a 26 ns access time. The short access time was realized using new circuit techniques combined with 1.0 µm CMOS technology. A new word line drive architecture realizes a short word line rise time despite a cell pitch which is smaller than the second Al pitch. To shorten the sensing time, a fully differential sensing circuit which enables reduced boron dose transistors to be used was adopted. A low noise output buffer is also used for achieving high speed operation while reducing the peak current noise.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_4_890/_p
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@ARTICLE{e74-c_4_890,
author={Yasuhiro HOTTA, Mikiro OKADA, Ryusuke MATSUYAMA, Hiroshi TSUGITA, Kenji SANO, Akihiko KUNIKANE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 26 ns 1 Mbit CMOS Mask ROM},
year={1991},
volume={E74-C},
number={4},
pages={890-895},
abstract={Recently, in response to the ever increasing speed of microprocessors, high speed operation has become an important requirement for mask ROM. This paper describes the circuit technologies used in a high speed mask ROM with a 26 ns access time. The short access time was realized using new circuit techniques combined with 1.0 µm CMOS technology. A new word line drive architecture realizes a short word line rise time despite a cell pitch which is smaller than the second Al pitch. To shorten the sensing time, a fully differential sensing circuit which enables reduced boron dose transistors to be used was adopted. A low noise output buffer is also used for achieving high speed operation while reducing the peak current noise.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A 26 ns 1 Mbit CMOS Mask ROM
T2 - IEICE TRANSACTIONS on Electronics
SP - 890
EP - 895
AU - Yasuhiro HOTTA
AU - Mikiro OKADA
AU - Ryusuke MATSUYAMA
AU - Hiroshi TSUGITA
AU - Kenji SANO
AU - Akihiko KUNIKANE
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1991
AB - Recently, in response to the ever increasing speed of microprocessors, high speed operation has become an important requirement for mask ROM. This paper describes the circuit technologies used in a high speed mask ROM with a 26 ns access time. The short access time was realized using new circuit techniques combined with 1.0 µm CMOS technology. A new word line drive architecture realizes a short word line rise time despite a cell pitch which is smaller than the second Al pitch. To shorten the sensing time, a fully differential sensing circuit which enables reduced boron dose transistors to be used was adopted. A low noise output buffer is also used for achieving high speed operation while reducing the peak current noise.
ER -
English
