New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.

This paper describes the Hierarchical Module Generation Technique capable of creating a high performance memory macrocell. The technique features: (a) automatic generation of macrocells with multi-level hierarchies that achieves the same performance as manually designed macrocells; (b) flexible configuration of macrocells in terms of word-length, bit-width, and cell-shape; and (c) equivalent logic description is created simultaneously with generated patterns that can be used for logic or delay simulation is ASIC design. Several kinds of memory macrocells have been developed as a library including a 1-port RAM, a 2-port RAM, and a ROM using 0.8-µm CMOS technology to verify the effectiveness of this technique.