IEICE TRANSACTIONS on Electronics
High-Performance Memory Macrocells with Row and Column Sliceable Architecture
Summary :
New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E76-C No.11 pp.1641-1648
- Publication Date
- 1993/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
- Application Specific Memory
Authors
Keyword
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Nobutaro SHIBATA, Yoshinori GOTOH, Shigeru DATE, "High-Performance Memory Macrocells with Row and Column Sliceable Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 11, pp. 1641-1648, November 1993, doi: .
Abstract: New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_11_1641/_p
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@ARTICLE{e76-c_11_1641,
author={Nobutaro SHIBATA, Yoshinori GOTOH, Shigeru DATE, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-Performance Memory Macrocells with Row and Column Sliceable Architecture},
year={1993},
volume={E76-C},
number={11},
pages={1641-1648},
abstract={New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - High-Performance Memory Macrocells with Row and Column Sliceable Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1641
EP - 1648
AU - Nobutaro SHIBATA
AU - Yoshinori GOTOH
AU - Shigeru DATE
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1993
AB - New memory-macrocell architecture has been developed to obtain high-performance macrocells with a short design Turn-Around-Time (TAT) in ASIC design. The authors propose row- and column-sliceable macrocell architecture in which only nine kinds of rectangular-functional cells, called leaf-cells, are abutted to form macrocells of any sizes. The row-sliceable structure of peripheral circuits is possible due to a newly-developed channel-embedded address decoder combined with via-hole programming. Macrocell performance, especially access time, is kept at a high level by the distributed driver configuration. Zero address-setup time during write operation is actualized by delaying internal write timing with a new delay circuit. A short design TAT of 30 minutes is accomplished due to the simplicity of both macrocell generation and the checking procedure. The macrocells are designed with gate-array and full-custom style, and fabricated with 0.5 µm CMOS technology.
ER -
English
