This paper describes the effect of lowering the supply voltage and threshold voltages on the energy reduction of an ultralow-voltage multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuit. The energy dissipation is evaluated using a graph with equispeed and equienergy lines on a supply voltage and a threshold voltage plane. In order to draw equispeed and equienergy lines for ultralow-voltage circuits, we propose a modified energy-evaluation model taking into account a input-waveform transition-time of the circuits. The validity of the proposed energy-evaluation model is confirmed by the evaluation of a gate-chain TEG and a 16-bit CLA adder fabricated with 0.25-µm MTCMOS/SIMOX technology. Using the modified model, the energy-reduction effect in lowering the supply voltage is evaluated for a single-Vth fully-depleted CMOS/SOI circuit, a dual-Vth CMOS circuit consisting of fully-depleted low- and medium-Vth MOSFETs, and a triple-Vth MTCMOS/SIMOX circuit. The evaluation reveals that lowering the supply voltage of the MTCMOS/SIMOX circuit to 0.5 V is advantageous for the energy reduction at a constant operating speed.

Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.

A 3 to 5-GHz Si-bipolar quadrature modulator and demodulator are described. Both feature a wideband frequency-doubling 90-degree phase shifter that has a mechanism for self-correction of phase errors caused by an original 90-degree phase-shift network at the half frequency of the carrier. Therefore, the phase shifter produces accurate quadrature carrier signals with doubled frequency. The quadrature modulator and demodulator in 30-GHz Si bipolar technology dissipate 80 mA at a 3-V supply. Image rejection of the modulator is more than 40 dB between 3.2 to 5.2 GHz. The phase and amplitude errors of the demodulator are less than 1.5 degrees and less than 0.15 dB, respectively, between 3.5 to 5.2 GHz. Therefore, both are suitable for either direct conversion or image-rejection transceivers for 5-GHz applications.

This paper describes the Hierarchical Module Generation Technique capable of creating a high performance memory macrocell. The technique features: (a) automatic generation of macrocells with multi-level hierarchies that achieves the same performance as manually designed macrocells; (b) flexible configuration of macrocells in terms of word-length, bit-width, and cell-shape; and (c) equivalent logic description is created simultaneously with generated patterns that can be used for logic or delay simulation is ASIC design. Several kinds of memory macrocells have been developed as a library including a 1-port RAM, a 2-port RAM, and a ROM using 0.8-µm CMOS technology to verify the effectiveness of this technique.

With the great leaps forward in standard memories like DRAMs and SRAMs, demands for a dedicated memory oriented to special applications have become increasingly strong. This paper presents the state of the art of ASIC memories, explaining the key points needed to implement additional features. Trends are outlined and technological issues concerning device choice, circuit technique, and design methodology are discussed. Through consideration of future trends in ASIC memories, it's clarified that achieving high-speed performance as well as high memory capacity with sophisticated logic fills most of the special applications.