Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology

Takakuni DOUSEKI; Shin'ichiro MUTOH; Takemi UEKI; Junzo YAMADA

Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology

Takakuni DOUSEKI, Shin'ichiro MUTOH, Takemi UEKI, Junzo YAMADA

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Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.2 pp.179-184

Publication Date: 1996/02/25

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Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)

Category: Device and Circuit Characterization

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Takakuni DOUSEKI, Shin'ichiro MUTOH, Takemi UEKI, Junzo YAMADA, "Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 2, pp. 179-184, February 1996, doi: .
Abstract: Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_2_179/_p

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@ARTICLE{e79-c_2_179,
author={Takakuni DOUSEKI, Shin'ichiro MUTOH, Takemi UEKI, Junzo YAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology},
year={1996},
volume={E79-C},
number={2},
pages={179-184},
abstract={Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 179
EP - 184
AU - Takakuni DOUSEKI
AU - Shin'ichiro MUTOH
AU - Takemi UEKI
AU - Junzo YAMADA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1996
AB - Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.
ER -