The search functionality is under construction.
The search functionality is under construction.

Author Search Result

[Author] Makoto TAKAHASHI(3hit)

1-3hit
  • Effect of Dimethylselenium Supply Rate on Growth of Cu(In, Ga)Se2 Films

    Masahiro TAHASHI  Kenji IINUMA  Hideo GOTO  Kenji YOSHINO  Makoto TAKAHASHI  Toshiyuki IDO  

     
    BRIEF PAPER-Semiconductor Materials and Devices

      Vol:
    E95-C No:7
      Page(s):
    1304-1306

    Polycrystalline Cu(In,Ga)Se2 (CIGS) films were prepared by heat treatment of metallic precursors using dimethylselenium (Se(CH3)2), which is a less hazardous Se source than H2Se gas. CIGS films were fabricated at various Se(CH3)2 supply rates. We investigated the effect of the Se(CH3)2 supply rate on the crystal phase and surface morphology of the films.

  • A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array

    Kazuhiro SAWADA  Toshinari TAKAYANAGI  Kazutaka NOGAMI  Makoto TAKAHASHI  Masanori UCHIDA  Yukiko ITOH  Tetsuya IIZUKA  

     
    PAPER-ASIC

      Vol:
    E74-C No:4
      Page(s):
    929-937

    A 369Kbit SRAM configurable up to four ports, namely, a Port-Configurable (PC) SRAM embedded in 235 KG track-free gate array has been newly developed. The chip fabricated with 0.5 µm double polysilicon and aluminum process technology showed 5 ns on-chip access time. This is considered to be one of the solutions for many applications that require memory system of high speed, large density and high flexibility in configuration such as number of ports, words and bits. The basic PC SRAM cell is a polysilicon resistor load SRAM cell with port customization terminals which are connected by standard gate array customization layers, first and second Al and via hole. In order that a high flexibility in column partitioning is available, a column-sliceable design is employed. Two column-sliceable sense amplifier, Trip Point Controlled CMOS (TPCC) sence amp and Symmetric Current Mirror (SCM) sense amp, are proposed to be laid out wihtin a single column pitch. One basic PC SRAM building block of 123 Kbit consists of 4 sets of decoders, 512 rows each, and 240 columns. For low power and high speed operation, double word line structure with section driving 40 columns are employed. Therefore, in addition to the port configurability, a high flexibility in row and column is available. The maximum word depth is 6 k words with 60 column single port memory. The maximum number of independently operating memory is twelve in case of single port. The chip contains three blocks of 369 kbit so that wide range of selection of cache, TLB and resistor files are integrated with MPU and other logic circuits.

  • Numerical Analysis of Beam-Expanders Integrated with Laser Diodes

    Makoto TAKAHASHI  Tsukuru OHTOSHI  Masahiro AOKI  Hiroshi SATO  Shinji TSUJI  Kazuhisa UOMI  Ken NAONO  

     
    PAPER-Semiconductor Lasers

      Vol:
    E83-C No:6
      Page(s):
    845-854

    Waveguide characteristics of beam-expanders integrated with laser diodes were numerically analyzed by the beam propagation method (BPM) or the finite-difference time-domain (FD-TD) method. It was demonstrated that the vertically and horizontally hybrid tapered structure or an optimized refractive index in the cladding layer improve the trade-off relationship between fiber coupling efficiency and lasing characteristics. It was also demonstrated that exponentially tapering stripe width can reduce device length without sacrificing device properties.