IEICE TRANSACTIONS on Electronics
A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array
Summary :
A 369Kbit SRAM configurable up to four ports, namely, a Port-Configurable (PC) SRAM embedded in 235 KG track-free gate array has been newly developed. The chip fabricated with 0.5 µm double polysilicon and aluminum process technology showed 5 ns on-chip access time. This is considered to be one of the solutions for many applications that require memory system of high speed, large density and high flexibility in configuration such as number of ports, words and bits. The basic PC SRAM cell is a polysilicon resistor load SRAM cell with port customization terminals which are connected by standard gate array customization layers, first and second Al and via hole. In order that a high flexibility in column partitioning is available, a column-sliceable design is employed. Two column-sliceable sense amplifier, Trip Point Controlled CMOS (TPCC) sence amp and Symmetric Current Mirror (SCM) sense amp, are proposed to be laid out wihtin a single column pitch. One basic PC SRAM building block of 123 Kbit consists of 4 sets of decoders, 512 rows each, and 240 columns. For low power and high speed operation, double word line structure with section driving 40 columns are employed. Therefore, in addition to the port configurability, a high flexibility in row and column is available. The maximum word depth is 6 k words with 60 column single port memory. The maximum number of independently operating memory is twelve in case of single port. The chip contains three blocks of 369 kbit so that wide range of selection of cache, TLB and resistor files are integrated with MPU and other logic circuits.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E74-C No.4 pp.929-937
- Publication Date
- 1991/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
- ASIC
Authors
Kazuhiro SAWADA
Toshinari TAKAYANAGI
Kazutaka NOGAMI
Makoto TAKAHASHI
Masanori UCHIDA
Yukiko ITOH
Tetsuya IIZUKA
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Kazuhiro SAWADA, Toshinari TAKAYANAGI, Kazutaka NOGAMI, Makoto TAKAHASHI, Masanori UCHIDA, Yukiko ITOH, Tetsuya IIZUKA, "A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 4, pp. 929-937, April 1991, doi: .
Abstract: A 369Kbit SRAM configurable up to four ports, namely, a Port-Configurable (PC) SRAM embedded in 235 KG track-free gate array has been newly developed. The chip fabricated with 0.5 µm double polysilicon and aluminum process technology showed 5 ns on-chip access time. This is considered to be one of the solutions for many applications that require memory system of high speed, large density and high flexibility in configuration such as number of ports, words and bits. The basic PC SRAM cell is a polysilicon resistor load SRAM cell with port customization terminals which are connected by standard gate array customization layers, first and second Al and via hole. In order that a high flexibility in column partitioning is available, a column-sliceable design is employed. Two column-sliceable sense amplifier, Trip Point Controlled CMOS (TPCC) sence amp and Symmetric Current Mirror (SCM) sense amp, are proposed to be laid out wihtin a single column pitch. One basic PC SRAM building block of 123 Kbit consists of 4 sets of decoders, 512 rows each, and 240 columns. For low power and high speed operation, double word line structure with section driving 40 columns are employed. Therefore, in addition to the port configurability, a high flexibility in row and column is available. The maximum word depth is 6 k words with 60 column single port memory. The maximum number of independently operating memory is twelve in case of single port. The chip contains three blocks of 369 kbit so that wide range of selection of cache, TLB and resistor files are integrated with MPU and other logic circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_4_929/_p
Copy
@ARTICLE{e74-c_4_929,
author={Kazuhiro SAWADA, Toshinari TAKAYANAGI, Kazutaka NOGAMI, Makoto TAKAHASHI, Masanori UCHIDA, Yukiko ITOH, Tetsuya IIZUKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array},
year={1991},
volume={E74-C},
number={4},
pages={929-937},
abstract={A 369Kbit SRAM configurable up to four ports, namely, a Port-Configurable (PC) SRAM embedded in 235 KG track-free gate array has been newly developed. The chip fabricated with 0.5 µm double polysilicon and aluminum process technology showed 5 ns on-chip access time. This is considered to be one of the solutions for many applications that require memory system of high speed, large density and high flexibility in configuration such as number of ports, words and bits. The basic PC SRAM cell is a polysilicon resistor load SRAM cell with port customization terminals which are connected by standard gate array customization layers, first and second Al and via hole. In order that a high flexibility in column partitioning is available, a column-sliceable design is employed. Two column-sliceable sense amplifier, Trip Point Controlled CMOS (TPCC) sence amp and Symmetric Current Mirror (SCM) sense amp, are proposed to be laid out wihtin a single column pitch. One basic PC SRAM building block of 123 Kbit consists of 4 sets of decoders, 512 rows each, and 240 columns. For low power and high speed operation, double word line structure with section driving 40 columns are employed. Therefore, in addition to the port configurability, a high flexibility in row and column is available. The maximum word depth is 6 k words with 60 column single port memory. The maximum number of independently operating memory is twelve in case of single port. The chip contains three blocks of 369 kbit so that wide range of selection of cache, TLB and resistor files are integrated with MPU and other logic circuits.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A 5 ns 369 kbit Port-Configurable Embedded SRAM with 0.5 µm CMOS Gate Array
T2 - IEICE TRANSACTIONS on Electronics
SP - 929
EP - 937
AU - Kazuhiro SAWADA
AU - Toshinari TAKAYANAGI
AU - Kazutaka NOGAMI
AU - Makoto TAKAHASHI
AU - Masanori UCHIDA
AU - Yukiko ITOH
AU - Tetsuya IIZUKA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1991
AB - A 369Kbit SRAM configurable up to four ports, namely, a Port-Configurable (PC) SRAM embedded in 235 KG track-free gate array has been newly developed. The chip fabricated with 0.5 µm double polysilicon and aluminum process technology showed 5 ns on-chip access time. This is considered to be one of the solutions for many applications that require memory system of high speed, large density and high flexibility in configuration such as number of ports, words and bits. The basic PC SRAM cell is a polysilicon resistor load SRAM cell with port customization terminals which are connected by standard gate array customization layers, first and second Al and via hole. In order that a high flexibility in column partitioning is available, a column-sliceable design is employed. Two column-sliceable sense amplifier, Trip Point Controlled CMOS (TPCC) sence amp and Symmetric Current Mirror (SCM) sense amp, are proposed to be laid out wihtin a single column pitch. One basic PC SRAM building block of 123 Kbit consists of 4 sets of decoders, 512 rows each, and 240 columns. For low power and high speed operation, double word line structure with section driving 40 columns are employed. Therefore, in addition to the port configurability, a high flexibility in row and column is available. The maximum word depth is 6 k words with 60 column single port memory. The maximum number of independently operating memory is twelve in case of single port. The chip contains three blocks of 369 kbit so that wide range of selection of cache, TLB and resistor files are integrated with MPU and other logic circuits.
ER -
English
