Delay time and power consumption, serious problems in high-density SRAM's are simulated over several generations with the HWD architecture. The optimum grade of hierarchy is obtaind for 64 kbit to 256 Mbit SRAM's.

This letter describes the fan-out optimization method of the SRAM decoder having line capacitance that minimizes the total delay time. It is shown that the total delay time of the SRAM decoder optimized by this mothod is less than that of the equal fan-out condition.

This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.

This paper describes the delay time on bit lines due to coupling capacitance between adjacent bit lines in megabit SRAM's. The delay time on bit lines in several generations of megabit SRAM's is quantitatively analyzed using device and circuit simulations. It is shown that narrowing the bit-line swing from 200 mV to 30 mV for future 16-Mbit SRAM's will effectively reduce the difference in delay time from 1.0 ns to 0.3 ns, and that a two-block devided bit line will lower the difference in the delay-time ratio to 3% in case of 15-ns access time.

A new soft-error phenomenon in which the soft-error rate (SER) decreases as cycle time becomes shorter has been found in static RAM's (SRAM's) employing a high-resistive load memory cell. This inverted dependence is observed during the read cycle in the SRAM's involving the PMOS bit-line load. The SER at the cycle time of 100 ns is reduced by 1.5-orders of magnitude compared with that of conventional SRAM's. The convertional dependence of SER on cycle time has been explained with the time constant to charge up the "High" storage node potential through the high-resistive load. The mechanism of the inverted dependence becomes clear in consideration of the time constant of the potential drop of the "High" storage node. The analysis is applied to explain that three kinds of dependence of SER on cycle time, which are the conventional dependence, the inverted dependence, and no dependence, will be observed when the following cell parameters are changed. One is the threshold voltage of driver transistors in the cell, and the other is the impedance of the high-resistive load.

We analyze the substrate corrent of submicron transistors in the memory cell of ULSI SRAMs in the cases of PMOS and NMOS bit line loads. The lifetime of the transistors is also estimated. The SRAM using an NMOS bit load is found to be better as a hot carrier than that with a PMOS bit load.