IEICE TRANSACTIONS on transactions
A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's
Summary :
Delay time and power consumption, serious problems in high-density SRAM's are simulated over several generations with the HWD architecture. The optimum grade of hierarchy is obtaind for 64 kbit to 256 Mbit SRAM's.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E73-E No.11 pp.1858-1860
- Publication Date
- 1990/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
- Category
- Integrated Circuits
Authors
Keyword
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Hirotoshi SATO, Shuji MURAKAMI, Yasumasa NISHIMURA, Toshihiko HIROSE, Kenji ANAMI, "A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's" in IEICE TRANSACTIONS on transactions,
vol. E73-E, no. 11, pp. 1858-1860, November 1990, doi: .
Abstract: Delay time and power consumption, serious problems in high-density SRAM's are simulated over several generations with the HWD architecture. The optimum grade of hierarchy is obtaind for 64 kbit to 256 Mbit SRAM's.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e73-e_11_1858/_p
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@ARTICLE{e73-e_11_1858,
author={Hirotoshi SATO, Shuji MURAKAMI, Yasumasa NISHIMURA, Toshihiko HIROSE, Kenji ANAMI, },
journal={IEICE TRANSACTIONS on transactions},
title={A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's},
year={1990},
volume={E73-E},
number={11},
pages={1858-1860},
abstract={Delay time and power consumption, serious problems in high-density SRAM's are simulated over several generations with the HWD architecture. The optimum grade of hierarchy is obtaind for 64 kbit to 256 Mbit SRAM's.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Study of Hierarchical Word Decoding Architecture for ULSI SRAM's
T2 - IEICE TRANSACTIONS on transactions
SP - 1858
EP - 1860
AU - Hirotoshi SATO
AU - Shuji MURAKAMI
AU - Yasumasa NISHIMURA
AU - Toshihiko HIROSE
AU - Kenji ANAMI
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 11
JA - IEICE TRANSACTIONS on transactions
Y1 - November 1990
AB - Delay time and power consumption, serious problems in high-density SRAM's are simulated over several generations with the HWD architecture. The optimum grade of hierarchy is obtaind for 64 kbit to 256 Mbit SRAM's.
ER -
English
