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A Study on Fanout Optimization of SRAM Decoder with a Line Capacitance

Shigeki OHBAYASHI, Tomohisa WADA, Toshihiko HIROSE, Kenji ANAMI

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Summary :

This letter describes the fan-out optimization method of the SRAM decoder having line capacitance that minimizes the total delay time. It is shown that the total delay time of the SRAM decoder optimized by this mothod is less than that of the equal fan-out condition.

Publication
IEICE TRANSACTIONS on transactions Vol.E73-E No.11 pp.1855-1857
Publication Date
1990/11/25
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section LETTER (Special Issue on 1990 Autumn Natl. Conv. IEICE)
Category
Integrated Circuits

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