A new soft-error phenomenon in which the soft-error rate (SER) decreases as cycle time becomes shorter has been found in static RAM's (SRAM's) employing a high-resistive load memory cell. This inverted dependence is observed during the read cycle in the SRAM's involving the PMOS bit-line load. The SER at the cycle time of 100 ns is reduced by 1.5-orders of magnitude compared with that of conventional SRAM's. The convertional dependence of SER on cycle time has been explained with the time constant to charge up the "High" storage node potential through the high-resistive load. The mechanism of the inverted dependence becomes clear in consideration of the time constant of the potential drop of the "High" storage node. The analysis is applied to explain that three kinds of dependence of SER on cycle time, which are the conventional dependence, the inverted dependence, and no dependence, will be observed when the following cell parameters are changed. One is the threshold voltage of driver transistors in the cell, and the other is the impedance of the high-resistive load.