IEICE TRANSACTIONS on Electronics
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
Summary :
This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.622-629
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.622
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Memory
Authors
Hideyuki NODA
Kazunari INOUE
Hans Jurgen MATTAUSCH
Tetsushi KOIDE
Katsumi DOSAKA
Kazutami ARIMOTO
Kazuyasu FUJISHIMA
Kenji ANAMI
Tsutomu YOSHIHARA
Keyword
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Hideyuki NODA, Kazunari INOUE, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Katsumi DOSAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, Kenji ANAMI, Tsutomu YOSHIHARA, "Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 622-629, April 2005, doi: 10.1093/ietele/e88-c.4.622.
Abstract: This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.622/_p
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@ARTICLE{e88-c_4_622,
author={Hideyuki NODA, Kazunari INOUE, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Katsumi DOSAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, Kenji ANAMI, Tsutomu YOSHIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh},
year={2005},
volume={E88-C},
number={4},
pages={622-629},
abstract={This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.},
keywords={},
doi={10.1093/ietele/e88-c.4.622},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
T2 - IEICE TRANSACTIONS on Electronics
SP - 622
EP - 629
AU - Hideyuki NODA
AU - Kazunari INOUE
AU - Hans Jurgen MATTAUSCH
AU - Tetsushi KOIDE
AU - Katsumi DOSAKA
AU - Kazutami ARIMOTO
AU - Kazuyasu FUJISHIMA
AU - Kenji ANAMI
AU - Tsutomu YOSHIHARA
PY - 2005
DO - 10.1093/ietele/e88-c.4.622
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dynamic TCAM (PD-TCAM) allows small cell size of 4.79 µm2 in 130 nm CMOS technology, and realizes stable TCAM operation even with very small storage capacitance. Due to the TSR architecture, the PD-TCAM maintains functional compatibility with a conventional SRAM-based TCAM. The combined effects of the compact PD-TCAM array matrix and the APM technique result in up to 50% reduction of the total power consumption during search operation. In addition, an intelligent address-input-free writing scheme is also introduced to facilitate the PD-TCAM application for the user. Consequently the proposed architecture is quite attractive for realizing compact and low-power embedded TCAM macros for the design of system VLSI solutions in the field of networking applications.
ER -
English
