Leakage Current Reduction in Surrounding Hi-Capacitor DRAM Cell
Summary :
Leakage current in SCC DRAM was reduced by optimizing implant conditions to form channel stopper, node connection and Hi-C boron. To reduce leakage current, the implantation doses should be reduced to reduce implant induced damages. These implant dose reductions are compromised to the necessities of high p type concentration to prevent punch-throughs at several parts of the cell. Near the deep trench bottom, damaged region due to Hi-C boron implant is separated from the bottom edge of the n+ storage node to suppress the gate controlled leakage current. By the improvements, the retention time of the 16 M SCC DRAM becomes over 30 sec at room temperature. It is also shown that folded bit line structure could be adopted easily for SCC.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E74-C No.4 pp.812-817
- Publication Date
- 1991/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
- DRAM
Authors
Geshu FUSE
Ichirou NAKAO
Yohei ICHIKAWA
Chiaki KUDO
Toshiki YABU
Akito UNO
Kazuyuki SAWADA
Yasushi NAITO
Michihiro INOUE
Hiroshi IWASAKI
Keyword
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Geshu FUSE, Ichirou NAKAO, Yohei ICHIKAWA, Chiaki KUDO, Toshiki YABU, Akito UNO, Kazuyuki SAWADA, Yasushi NAITO, Michihiro INOUE, Hiroshi IWASAKI, "Leakage Current Reduction in Surrounding Hi-Capacitor DRAM Cell" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 4, pp. 812-817, April 1991, doi: .
Abstract: Leakage current in SCC DRAM was reduced by optimizing implant conditions to form channel stopper, node connection and Hi-C boron. To reduce leakage current, the implantation doses should be reduced to reduce implant induced damages. These implant dose reductions are compromised to the necessities of high p type concentration to prevent punch-throughs at several parts of the cell. Near the deep trench bottom, damaged region due to Hi-C boron implant is separated from the bottom edge of the n+ storage node to suppress the gate controlled leakage current. By the improvements, the retention time of the 16 M SCC DRAM becomes over 30 sec at room temperature. It is also shown that folded bit line structure could be adopted easily for SCC.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_4_812/_p
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@ARTICLE{e74-c_4_812,
author={Geshu FUSE, Ichirou NAKAO, Yohei ICHIKAWA, Chiaki KUDO, Toshiki YABU, Akito UNO, Kazuyuki SAWADA, Yasushi NAITO, Michihiro INOUE, Hiroshi IWASAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Leakage Current Reduction in Surrounding Hi-Capacitor DRAM Cell},
year={1991},
volume={E74-C},
number={4},
pages={812-817},
abstract={Leakage current in SCC DRAM was reduced by optimizing implant conditions to form channel stopper, node connection and Hi-C boron. To reduce leakage current, the implantation doses should be reduced to reduce implant induced damages. These implant dose reductions are compromised to the necessities of high p type concentration to prevent punch-throughs at several parts of the cell. Near the deep trench bottom, damaged region due to Hi-C boron implant is separated from the bottom edge of the n+ storage node to suppress the gate controlled leakage current. By the improvements, the retention time of the 16 M SCC DRAM becomes over 30 sec at room temperature. It is also shown that folded bit line structure could be adopted easily for SCC.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Leakage Current Reduction in Surrounding Hi-Capacitor DRAM Cell
T2 - IEICE TRANSACTIONS on Electronics
SP - 812
EP - 817
AU - Geshu FUSE
AU - Ichirou NAKAO
AU - Yohei ICHIKAWA
AU - Chiaki KUDO
AU - Toshiki YABU
AU - Akito UNO
AU - Kazuyuki SAWADA
AU - Yasushi NAITO
AU - Michihiro INOUE
AU - Hiroshi IWASAKI
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1991
AB - Leakage current in SCC DRAM was reduced by optimizing implant conditions to form channel stopper, node connection and Hi-C boron. To reduce leakage current, the implantation doses should be reduced to reduce implant induced damages. These implant dose reductions are compromised to the necessities of high p type concentration to prevent punch-throughs at several parts of the cell. Near the deep trench bottom, damaged region due to Hi-C boron implant is separated from the bottom edge of the n+ storage node to suppress the gate controlled leakage current. By the improvements, the retention time of the 16 M SCC DRAM becomes over 30 sec at room temperature. It is also shown that folded bit line structure could be adopted easily for SCC.
ER -
English
