Leakage current in SCC DRAM was reduced by optimizing implant conditions to form channel stopper, node connection and Hi-C boron. To reduce leakage current, the implantation doses should be reduced to reduce implant induced damages. These implant dose reductions are compromised to the necessities of high p type concentration to prevent punch-throughs at several parts of the cell. Near the deep trench bottom, damaged region due to Hi-C boron implant is separated from the bottom edge of the n+ storage node to suppress the gate controlled leakage current. By the improvements, the retention time of the 16 M SCC DRAM becomes over 30 sec at room temperature. It is also shown that folded bit line structure could be adopted easily for SCC.

This paper describes a key technology of a small sized stacked capacitor cell to realize 16 MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, which provides reliable contacts with high immunity against process fluctuations such as overetching side-etching and pattern misalignment in photolithography. The cell made by this technology showed desirable characteristics for DRAM operation.