Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM
Summary :
This paper describes a key technology of a small sized stacked capacitor cell to realize 16 MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, which provides reliable contacts with high immunity against process fluctuations such as overetching side-etching and pattern misalignment in photolithography. The cell made by this technology showed desirable characteristics for DRAM operation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E74-C No.4 pp.818-826
- Publication Date
- 1991/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
- DRAM
Authors
Masanori FUKUMOTO
Yasushi NAITO
Kazuhiro MATSUYAMA
Hisashi OGAWA
Koji MATSUOKA
Takashi HORI
Hiroyuki SAKAI
Ichiro NAKAO
Hisakazu KOTANI
Hiroshi IWASAKI
Michihiro INOUE
Keyword
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Masanori FUKUMOTO, Yasushi NAITO, Kazuhiro MATSUYAMA, Hisashi OGAWA, Koji MATSUOKA, Takashi HORI, Hiroyuki SAKAI, Ichiro NAKAO, Hisakazu KOTANI, Hiroshi IWASAKI, Michihiro INOUE, "Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 4, pp. 818-826, April 1991, doi: .
Abstract: This paper describes a key technology of a small sized stacked capacitor cell to realize 16 MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, which provides reliable contacts with high immunity against process fluctuations such as overetching side-etching and pattern misalignment in photolithography. The cell made by this technology showed desirable characteristics for DRAM operation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_4_818/_p
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@ARTICLE{e74-c_4_818,
author={Masanori FUKUMOTO, Yasushi NAITO, Kazuhiro MATSUYAMA, Hisashi OGAWA, Koji MATSUOKA, Takashi HORI, Hiroyuki SAKAI, Ichiro NAKAO, Hisakazu KOTANI, Hiroshi IWASAKI, Michihiro INOUE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM},
year={1991},
volume={E74-C},
number={4},
pages={818-826},
abstract={This paper describes a key technology of a small sized stacked capacitor cell to realize 16 MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, which provides reliable contacts with high immunity against process fluctuations such as overetching side-etching and pattern misalignment in photolithography. The cell made by this technology showed desirable characteristics for DRAM operation.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 818
EP - 826
AU - Masanori FUKUMOTO
AU - Yasushi NAITO
AU - Kazuhiro MATSUYAMA
AU - Hisashi OGAWA
AU - Koji MATSUOKA
AU - Takashi HORI
AU - Hiroyuki SAKAI
AU - Ichiro NAKAO
AU - Hisakazu KOTANI
AU - Hiroshi IWASAKI
AU - Michihiro INOUE
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1991
AB - This paper describes a key technology of a small sized stacked capacitor cell to realize 16 MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, which provides reliable contacts with high immunity against process fluctuations such as overetching side-etching and pattern misalignment in photolithography. The cell made by this technology showed desirable characteristics for DRAM operation.
ER -
English
