The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

A novel logic functional level converter (FLC) was developed to achieve a high speed ECL I/O BiCMOS SRAM. The FLC simultaneously enables high speed logic operation and ECL to CMOS level conversion. This paper describes an optimized design method for the FLC and an improved FLC. In addition, a high speed partial decoding level converter (PDLC), composed of improved FLCs, is presented. The FLC and a newly developed address decoding sheme with PDLCs, are keys to the successful production of the 5ns 1Mb ECL I/O BiCMOS SRAM.

PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducting the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.

This paper reviews the progresses of static random access memories (SRAMs) for the last past 10 years and shows how much memory cell sizes have been reduced and how the chip sizes have increased to increase memory capacities. After a basic SRAM chip organization is briefly described for readers' convenience, various latest and important key technologies for CMOS, bipolar transistor and BiCMOS SRAMs are reviewed. Chip organizations and circuit technologies to improve performance, which have been used in recently reported high performance SRAMs, are also introduced. Future large scale and high speed SRAMs are also forecasted.

A 65 Kbit dynamic MOSRAM has been realized using short channel and single-level Si-gate technologies and a newly designed, highly sensitive and low power dissipation sense amplifier. Access time and power dissipation are 150 ns and 120 mW, respectively.

We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and VOH/VOL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.