PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs
Summary :
PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducting the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.805-811
- Publication Date
- 1995/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
- Category
Authors
Kazuyuki NAKAMURA
Shigeru KUHARA
Thoru KIMURA
Masahide TAKADA
Hisamitsu SUZUKI
Hiroshi YOSHIDA
Tohru YAMAZAKI
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Kazuyuki NAKAMURA, Shigeru KUHARA, Thoru KIMURA, Masahide TAKADA, Hisamitsu SUZUKI, Hiroshi YOSHIDA, Tohru YAMAZAKI, "PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 7, pp. 805-811, July 1995, doi: .
Abstract: PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducting the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_7_805/_p
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@ARTICLE{e78-c_7_805,
author={Kazuyuki NAKAMURA, Shigeru KUHARA, Thoru KIMURA, Masahide TAKADA, Hisamitsu SUZUKI, Hiroshi YOSHIDA, Tohru YAMAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs},
year={1995},
volume={E78-C},
number={7},
pages={805-811},
abstract={PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducting the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs
T2 - IEICE TRANSACTIONS on Electronics
SP - 805
EP - 811
AU - Kazuyuki NAKAMURA
AU - Shigeru KUHARA
AU - Thoru KIMURA
AU - Masahide TAKADA
AU - Hisamitsu SUZUKI
AU - Hiroshi YOSHIDA
AU - Tohru YAMAZAKI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme for reducting the access time and the memory cell current, (2) a cyclic input buffer power-cutting scheme to reduce the excess power in low-frequency operation, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers to reduce the test costs. These techniques successfully contribute to the development of a 7 ns GTL I/O 16 Mb BiCMOS SRAM LSI.
ER -
English
