BIST Circuit Macro Using Microprogram ROM for LSI Memories

Hiroki KOIKE; Toshio TAKESHIMA; Masahide TAKADA

BIST Circuit Macro Using Microprogram ROM for LSI Memories

Hiroki KOIKE, Toshio TAKESHIMA, Masahide TAKADA

Full Text Views

0

Cite this

Summary :

We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and V_OH/V_OL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.838-844

Publication Date: 1995/07/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)

Category

Cite this

Copy

Hiroki KOIKE, Toshio TAKESHIMA, Masahide TAKADA, "BIST Circuit Macro Using Microprogram ROM for LSI Memories" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 7, pp. 838-844, July 1995, doi: .
Abstract: We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and V_OH/V_OL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_7_838/_p

Copy

@ARTICLE{e78-c_7_838,
author={Hiroki KOIKE, Toshio TAKESHIMA, Masahide TAKADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={BIST Circuit Macro Using Microprogram ROM for LSI Memories},
year={1995},
volume={E78-C},
number={7},
pages={838-844},
abstract={We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and V_OH/V_OL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.},
keywords={},
doi={},
ISSN={},
month={July},}

Copy

TY - JOUR
TI - BIST Circuit Macro Using Microprogram ROM for LSI Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 838
EP - 844
AU - Hiroki KOIKE
AU - Toshio TAKESHIMA
AU - Masahide TAKADA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - We developed an on-chip memory tester macro using a microprogram ROM BIST circuit. Only slight modification of address buffers, data bus I/O circuits and control clock generators of the memory core circuits was required to implement this BIST macro. We fabricated a 1 Mb DRAM with the BIST, and experimental results showed that the measured shmoo plot of VCC versus the cycle time by the BIST closely agreed with that of a memory tester. Disagreement was caused by test address signal set-up time delay and V_OH/V_OL differences in both test conditions. The BIST macro will be especially useful for design-for-testability of embedded memories.
ER -