We have manufactured large-scaled highly reliable MNOS EEPROMs over the last twenty years. In particular, at the present time, the smart-card microcontroller incorporating an embedded 32-kB MNOS EEPROM is rapidly expanding the markets for mobile applications. It might be said that we have established the conventional MNOS nonvolatile semiconductor memory technology. This paper describes the device design concepts of the MNOS memory, which include the optimization and control of the tunnel oxide film thickness (1.8 nm), and the scaling guideline that considers the charge distribution in the trapping nitride film. We have developed a high-performance MONOS structure and have not found any failure due to the MONOS devices in high-density EEPROM products during 10-year data retention tests after 105 erase/write cycles. The future development of this highly reliable MNOS-type memory will be focussed on the high-density cell structure and high-speed programming method. Recently, some promising ideas for utilizing an MNOS-type memory device, such as 1-Tr/bit cell for byte-erasable full-featured EEPROMs and 2-bit/Tr cell for flash EEPROMs have been proposed. We are convinced that MNOS technology will advance into the area of nonvolatile semiconductor memories because of its high reliability and high yield of products.

The optimal tunnel oxide thickness in MNOS memory devices is determined for the first time to be 1.8 nm0.1 nm, by considering ten-year data retention after 105 erase/write cycles at a temperature of 85. It is also demonstrated that the tunnel oxide thickness can remain constant, regardless of the extent of scaling down of MNOS memory devices, as long as the programming time is kept constant at 10 ms. In addition, we derive the programming electric field to be 4.2-5.1 MV/cm in the silicon nitride for MNOS design. As a result, a new authentic MNOS design concept is presented.

A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.