IEICE TRANSACTIONS on Electronics
A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology
Summary :
A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.8 pp.1260-1269
- Publication Date
- 1994/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
- Category
- Non-volatile Memory
Authors
Keyword
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Shin-ichi MINAMI, Kazuaki UJIIE, Masaaki TERASAWA, Kazuhiro KOMORI, Kazunori FURUSAWA, Yoshiaki KAMIGAKI, "A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 8, pp. 1260-1269, August 1994, doi: .
Abstract: A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_8_1260/_p
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@ARTICLE{e77-c_8_1260,
author={Shin-ichi MINAMI, Kazuaki UJIIE, Masaaki TERASAWA, Kazuhiro KOMORI, Kazunori FURUSAWA, Yoshiaki KAMIGAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology},
year={1994},
volume={E77-C},
number={8},
pages={1260-1269},
abstract={A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A 3 Volt 1 Mbit Full-Featured EEPROM Using a Highly-Reliable MONOS Device Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 1260
EP - 1269
AU - Shin-ichi MINAMI
AU - Kazuaki UJIIE
AU - Masaaki TERASAWA
AU - Kazuhiro KOMORI
AU - Kazunori FURUSAWA
AU - Yoshiaki KAMIGAKI
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1994
AB - A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm2 and a memory cell size of 23.1µm2. An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 106 erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.
ER -
English
