We compare interfaces of Nb/AlO_x-Al/Nb and Nb/ZrO_x-Zr/Nb junctions using secondary ion mass spectroscopy and cross-sectional transmission electron microscopy. We have clarified that an interface of the Nb/AlO_x-Al/Nb junction is drastically different from that of the Nb/ZrO_xZr/Nb junction. An adsorbed water vapor layer plays an important role in suppressing grain boundary diffusion between Nb and Al at the interface of the Nb/AlO_xAl/Nb junction. In depositing Nb and Al at low power and cooling the substrate, it is important to control the formation of the adsorbed water vapor layer for fabricating Nb/AlO_x-Al/Nb junctions exhibiting excellent current-voltage characteristics.

A superconducting multichip module using Nb/Polyimide on a mullite multilayer ceramic substrate has been developed for Josephson LSI circuits. The Nb/Polyimide stacked layers on the mullite multilayer ceramic substrate makes it possible to fabricate superconducting off-chip wiring for control signal line. We named the MCM "SuperMCM". The superconducting transmission line is designed to have the characteristic impedance of 14 Ω to match with the Josephson devices. The superconducting critical temperature, critical current density and critical current at a via hole are 8.5 K, 8.210⁵ A/cm² and 2.5 A, respectively. The SuperMCM also provides matching circuits employing quarter wavelength striplines for driving Josephson LSI circuits at a microwave frequency, and DC bias circuits in the mullite multilayer ceramic substrate. The characteristics of the matching circuit is measured in the frequency range up to 3.6 GHz and the microwave current gain of 20 dB is obtained at 1.2 GHz, which revealed that the SuperMCM has the ability to drive the Josephson LSI circuits at more than 1.2 GHz clock speed.

We have fabricated Nb/AlO_x/Nb Josephson tunnel junctions by a sputtering apparatus with a load-lock system. This sputtering apparatus had the sub chamber for preparation and the main chamber for sputtering. The substrate temperature was confirmed to be kept less than 85 during Nb sputtering at the deposition rate of 1.18 nm/s for 7 minutes. The junctions that had 50µm50 µm area successfully showed the V_m value (the product of the critical current and the subgap resistance at 2 mV) as high as 50 mV at the current density of 100 A/cm².

The magnitude of low frequency noise is studied in a Nb-(nanoconstrictions)-NbN system with adjustable current-voltage characteristics. We find that the magnitude of low frequency noise decreases sharply with increasing the subgap conductivity of the device. We suggest a qualitative explanation of this observation in terms of gradual build up of the nanoconstriction region by field assisted growth. The decrease of low frequency noise is related to the "cleanliness" of the system as measured by the amount of Andreev reflection-related conductivity. The scaling of the magnitude of low frequency noise with device resistance is also discussed.

A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlO_x/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO₂ insulators. The Nb/AlO_x/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.

Microwave characteristics of a LiNbO₃ optical modulator using a superconductor (Pb-In-Au) as a resonant electrode has been studied experimentally at low temperatures down to 4.2 K. It is shown that at the resonance frequency of 14.8 GHz the obtained modulation depth takes a maximum value as expected from theory when the electrode becomes superconducting. The present results demonstrate the possible applications of superconducting electrodes to high performance LiNbO₃ optical modulators.

A multi-channel high temperature superconducting interference device (high T_c SQUID) system with high magnetic field resolution has been developed. Step edge junctions were employed as weakly coupled Josephson junctions for the SQUID. These junctions worked well and their I-V curves fit the resistively shunted junction (RSJ) model. The SQUID design was investigated to improve magnetic field resolution. The size of the SQUID's center hole was investigated, and we found the optimized size of the hole to be about 25 µm. Meissner effect of superconductor was used in order to concentrate magnetic fluxes. A large washer SQUID and a flux concentrating plate was developed to concentrate magnetic flux to the SQUID center hole. The magnetic field resolution became 370 fT/Hz at 10 Hz and 220 fT/Hz at 10 kHz. This field resolution was enough to detect biomagnetic signals such as magnetocardiac signals. The SQUID was mounted on a special chip carrier and was sealed with epoxy resin for protection from humidity. We have designed and developed a 4-channel and a 16-channel high T_c SQUID system. We used them in a magnetically shielded room to measure magnetic signals of the human heart. We obtained clear multi-channel magnetocardiac signals, which showed clear so called QRS and T wave peaks. A clear isofield contour map of magnetocardiac signals was also obtained. These data indicated that high T_c SQUID is feasible for these biomagnetic applications.

We have systematically grown and characterized (Bi, Pb)₂Sr₂CaCu₂O_y (BPSCCO) single crystals, and investigated the tunneling properties and the intrinsic Josephson effects of the single crystals as a function of the nominal composition of Pb, x. It was observed that Pb atoms (ions) were monotonically substituted for Bi atoms (ions) in the (Bi, Pb)-O layers of the crystals with increasing x in a region of 0x0.5, while the modulation structure was maintained in a range of 0x0.3, but disappeared in x0.3, accompanying the decrease of c-lattice parameter and T_c. Moreover, it was found that the energy gaps Δ of BPSCCO depend hardly on x for x0.5, which are about 24 meV, so that the Pb-induced electronic change in the (Bi, Pb)-O layer do not perturb the electronic states in this superconducting system. And it was confirmed that the currentvoltage characteristics of the BPSCCO single crystals had multiple resistive branches corresponding to a series array of several hundreds Josephson junctions, and showed Shapiro steps and zero-crossing steps with the voltage separation of the order of mV resulting from the phase locking of about a hundred Josephson junctions among them under microwave irradiation. The estimated number of junctions gave the concept that the intrinsic Josephson junctions consist of the superconducting block layers and the insulating layers in the BPSCCO single crystals.

Fabrication of all-epitaxial high-T_c SIS tunnel junctions requires an atomically flat superconducting thin film to be grown and a proper insulating material to be selected. First, we study the initial growth mode of YBCO thin films and show that reducing the growth rate results in a very smooth surface. Second, perovskite-related compound oxides, PrGaO₃ and NdGaO₃, which have a small lattice mismatch with YBCO and good wetability, are shown to be promising insulating materials for all-epitaxial SIS tunnel junctions. We believe that these concepts will be useful in the development of all-epitaxial high-T_c SIS tunnel junctions with good electrical properties.

This paper describes a new method for joining BiSrCaCuO superconductors (BSCCO) which realizes low microwave loss and high mechanical strength. This method consists of two processes. In the first the BSCCO surface is metallized with Ag and in the second a joint is formed by using thermally curable Ag paste. With this method, we obtained a joint with a loss of 0.3 dB around 1.1 GHz with the co-axial cavity techniques. Furthermore, the mechanical strength of the joint was greater than that of the BSCCO sample. From the results of DC resistance measurements and SEM observations, we attribute this good performance to the adhesion and continuity of the metallized Ag with the BSCCO surface.

Almost stoichiometric YBa₂Cu₃O_7-δ(110) or (103) and SrTiO_x(110) films, and multilayer films consisting of them have successfully been grown epitaxially on hot SrTiO₃ substrates by 90off-axis rf magnetron sputtering with facing targets. Their whole composition, compositional distribution in depth, crystallinity and surface morphology were examined by inductively coupled plasma spectroscopy, Auger electron spectroscopy, reflection high-energy electron diffraction, and scanning tunneling microscopy or atomic force microscope, respectively. When any YBa₂Cu₃O_7-δ film was exposed to air after deposition, a Ba-rich layer was formed in a near surface region of the film. However, such a compositional distribution in depth of the film was improved by in situ deposition of a SrTiO_x film on it. Moreover, the surface roughness of the YBa₂Cu₃O_7-δ film was improved by predeposition of a SrTiO_x film under it. On the basis of these results, both YBa₂Cu₃O_7-δ/SrTiO_x/YBa₂Cu₃O_7-δ/SrTiO₃(sub.) and YBa₂Cu₃O_7-δ/SrTiO_x/YBa₂Cu₃O_7-δ/SrTiO_x/SrTiO₃(sub.) multilayer films with average surface roughness of 3 nm were grown reproducibly, which had uniform compositional distribution throughout the depth of the film except a near surface region of the top YBa₂Cu₃O_7-δ layer. A new 222 structure described by Sr₈Ti₈O₂₀ (Sr₂Ti₂O₅) with a long range ordered arrangement of oxygen vacancies was formed in the SrTiO_x films deposited epitaxially on YBa₂Cu₃O_7-δ films.

Step-edge Josephson junctions (SEJJs), which are made by YBa₂Cu₃O₇ (YBCO) thin films on MgO (100) substrates with gentle step angle (below 40 degrees) have been successfully fabricated. The step-edge, with several angles on the MgO substrate, were made using photolithography and Ar ion beam etching, and then YBCO films were deposited on the step-edges by pulsed laser deposition method. The relationships between step-angles and I-V characteristics, microwave properties and structure of SEJJs were systematically investigated. Shapiro steps were clearly observed only in step-angle range between 10 and 30 degrees. Intermittence and hysteresis on the I-V characteristics were observed above 30 mA without effect from step-angles.

High temperature superconductors are eminently suitable for use in high frequency devices because of their large energy gap. We fabricated weak link Josephson junctions connected in series. The junctions were constructed of EuBa₂Cu₃O_7-x (EBCO) superconducting thin films on bicrystal MgO substrates. We measured their microwave broadband detection (video detection) characteristics. The responsivity (S_r) of the junctions depended on the bias current and their normal state resistance. The array junctions were effective in increasing normal state resistance. We obtained a maximum S_r of 22.6 [V/W].

This paper reports on the properties of thin-film thermal switches that are monolithically fabricated on high-T_c superconductive filter. Operating at a wide temperature range of 50-77 K, it was found that the switch could control the center frequency by -10 MHz with an increased insertion loss of less than 0.7 dB. In an on-off switching operation of filter characteristics using thin-film switches, power consumption was approximately 20 mW at 77 K, and the signal decay time as a switching speed was 30 ms at 76 K with a switch current of 70 mA. The decay time decreased exponentially as the switch current or the temperature setting increased.

A method using the microstrip line resonator is applied to measurements of the dielectric properties of a substrate and the surface resistance of a conducting strip line versus the frequency as well as the temperature. The variational expressions for the capacitance per unit length of several microstrip lines such as an inverted microstrip line and multi-layer microstrip lines are derived. The expression involves an integral along a semi-infinite interval, but the numerical integration is very easy. Effects of a buffer layer deposited on the substrate are investigated by using a multi-layer microstrip line model. The permittivity and the loss tangent of several dielectric materials are measured by the MSL and the IMSL or the multi-layer microstrip resonator. The measured surface resistance of copper and iron is also presented to show the validity of the present method. The surface resistance of a BSCCO thick film is also presented.

In this paper, we analyze high-T_c superconducting (HTS) microstrip antenna (MSA) using modified spectral domain moment method. Although it is assumed that the patch and the ground plane of the MSA are perfect electric conductors (PECs) in the conventional spectral domain method, we modify this method to compute the conduction loss of the HTS-MSA. In our analysis, the effect of the HTS film is introduced by the surface impedance which we can estimate by using the three fluid model and experimental results. This paper presents numerical results about the HTS-MSA, for example, the relations between the thickness of the substrate and the radiation efficiency, the temperature and the resonant frequency, and so forth. And we discuss the effective power range where the performance of the HTS-MSA is superior to that of the Cu-MSA.

This paper presents the history of Flash memories and the basic concept of their functions and also reviews a variety of Flash EEPROM's so far. As Flash memories have two influential features, non-volatility and low cost per bit, they are expected to become a driving force after DRAM's to support the semiconductor industry for the next thirty years, replacing hard and floppy disks which have a large market.

A low-voltage operation and highly-reliable nonvoltatile semiconductor memory with a large capacity has been manufactured using 0.8-µm CMOS technology. This 3-volt, 1-Mbit, full-featured MONOS EEPROM has a chip size of 51.3 mm² and a memory cell size of 23.1µm². An asymmetric programming voltage method fully exploits the abilities of the MONOS device and provides 10-year data retention after 10⁶ erase/write cycles. Because of its wide-margin circuit design, this EEPROM can also be operated at 5 volts. High-speed read out is provided by using the polycide word line and the differential sense amplifier with a MONOS dummy memory. New functions such as data protection with software and programming-end indication with a toggle bit are added, and chips are TSOP packaged for use in many kinds of portable equipment.

We propose, for the first time, highly reliable flash-type EEPROM cell fabrication using in-situ multiple rapid thermal processing (RTP) technology. In this study, rapid thermal oxynitridation tunnel oxide (RTONO) film formations followed by in-situ arsenic (As)-doped floating-gate polysilicon growth by rapid thermal chemical vapor deposition (RTCVD) technologies are fully utilized. The results show that after 510⁴ program/erase (P/E) endurance cycles, the conventional cell shows 65% narrowing of the threshold voltage (V_t) window, whereas the RTONO cell indicates narrowing of less than 20%. A large number of nitrogen atoms (10²⁰ atoms/cm³) are confirmed by secondary ion mass spectrometry (SIMS), pile up at the SiO₂/Si interface and distribute into bulk SiO₂. It is considered that in the RTONO film stable Si-N bonds are formed which minimize electron trap generation as well as the neutral defect density, resulting in lower V_t shifts in P/E stress. In addition, the RTONO film reduces the number of hydrogen atoms because of final N₂O oxynitridation. The SIMS data shows that by the in-situ RTCVD process As atoms (910²⁰ atoms/cm³) are incorporated uniformly into 1000--thick film. Moreover, the RTCVD polysilicon film indicates an extremely flat surface. The time-dependent dielectric breakdown (TDDB) characteristics of interpoly oxide-nitride-oxide (ONO) film exhibited no defect-related breakdown and 5 times longer breakdown time as compared to phosphorus-doped polysilicon film. Therefore, the flash-EEPROM cell fabricated has good charge storing capability.

A novel operation of a flash memory cell, named DINOR (DIvided bit line NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic cell characteristics such as program/erase, disturb immunity and a cycling endurance. Making a good use of this cell operation, we also proposed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 µm² cell size, suitable for 32 Mbit flash memory based on 0.5 µm CMOS process. In the last part of this paper, the useful and practical application of the DINOR operation to a virtual ground array architecture, realizing 1.0 µm² cell size for a 0.5 µm 64 Mbit flash memory, is described.

The data retention characteristics of a Flash memory cell with a self-aligned double poly-Si stacked structure have been drastically improved by applying a bi-polarity write and erase technology which uses uniform Fowler-Nordheim tunneling over the whole channel area both during write and erase. It is clarified experimentally that the detrapping of electrons from the gate oxide to the substrate results in an extended retention time. A bi-polarity write and erase technology also guarantees a wide cell threshold voltage window even after 10⁶ write/erase cycles. This technology results in a highly reliable EEPROM with an extended data retention time.

A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm² cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.

The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

This paper describes the architecture and new circuit technologies of a proposed Pixel (bit) -Aligned Triple-port DRAM (PATDRAM). The PATDRAM has a 270 K word 16 b Random Access Memory (RAM), a 512 word 8 b Serial Access Memory-(a) (SAMa) and a 1024 word 4 b Serial Access Memory-(b) (SAMb). The random port, serial-a and serial-b port can be operated by three independent synchronous clocks. In these three ports, word data can be aligned to the location of an arbitrary bit position. Data transfer from SAMb to RAM can be individually masked by transfer mask data. The RAM operates by 33 MHz synchronous clock and two SAMs operate by 40 MHz clocks. Novel architecture of the PATDRAM accelerates graphics performance and simplifies in multimedia systems which manage both realtime video and computer graphics data, and also accelerates graphics performance in both two-dimensional (2D) and three-dimensional (3D) graphics systems. PATDRAM was designed using a 0.6 µ double metal, triple poly, stacked capacitor, CMOS process technology in a 10.98 mm9.88 mm die area integrated 4.4 Mb RAM, 8 Kb SAM, 4 Kb transfer mask register and 5 Kgate logic.

A distributive serial multi-bit parallel test scheme for large capacity DRAMs has been developed. The scheme, distributively and serially, extracts and compares the data from cells on a main word-line. This test scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM, the scheme successfully has achieved a 512-bit parallel test.

A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180 MHz clock rate with area penalty of only 5.4% over the conventional DRAM.

Circuit techniques for realizing fast cycle time of DRAM are described. 1) A high-speed and high-efficiency word-line level V_pp supply can be obtained by a unique static CMOS double-boosted level generator (SCDB) which controls the V_pp charge supply gate. 2) A new write-control scheme eliminates the timing overhead of a read access time after write cycle in a fast page mode operation. 3) A floor plan that minimizes the load of signal paths by employing the lead-on-chip (LOC) assembly technique. These techniques are implemented in an address-multiplexed 16 Mbit CMOS DRAM using a 0.5-µm CMOS technology. A 31-ns RAS cycle time and a 19-ns fast page mode cycle time at V_cc3.3 V, and also even at V_cc1.8 V, a 53-ns RAS cycle time and a 32-ns fast page mode cycle time were achieved. This DRAM is applicable to battery-operated computing tools.

The progress of LSI technologies makes it possible to fabricate 256 MDRAM. However, it depends on the cost effectiveness of device fabrication that LSI memory can continue to be the technology driver or not. It is indispensable to make the device, process, and equipment as simple as possible for next generation LSI. For example, wavefront technologies in lithography, high energy ion implantation, and simple DRAM cell with SOI structure or high dielectric constant capacitor, are under development to satisfy both device performance improvement and process simplicity.

Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

A novel isolation structure which has a buried insulator between polysilicon electrodes (BIPS) has been developed. The BIPS isolation employs the refilling CVD-oxides in openings between polysilicon electrodes by photoresist etchback process. Device characteristics and parasitic effects of BIPS isolation have been compared with that of LOCOS isolation. Using BIPS isolation, we can almost suppress the narrow-channel effects and achieve the deep submicron isolation. No degradation on the subthreshold decay of devices with BIPS isolation can be obtained. The use of BIPS isolation technology yields a DRAM cell of small area. The successful fabrication of deep submicron devices with BIPS isolation clearly demonstrates that this technology has superior ability to overcome the LOCOS isolation.

New circuit techniques were proposed to realize a high-density and high-performance content addressable memory (CAM). A dynamic register which functions as a status flag, and some logic circuits are organically combined and flexibly perform complex search operations, despite the compact layout area. Any kind of logic operations for the search results, that are AND, OR, INVERT, and the combinations of them, can be implemented in every word simultaneously. These circuits are implemented in an experimental 288 kbit dynamic CAM using 0.8 µm CMOS process technology. We consider these techniques to be indispensable for high-density and high-performance dynamic CAM.

A full CMOS cell technology for high density SRAMs has been developed. A 0.4 µm n⁺/p⁺ spacing has been achieved by a shallow trench isolation with a retrograde and a shallow well design. Dual gate 0.35 µm n- and p-channel MOSFETs were used for the high density full CMOS SRAM cell. The side-wall inversion problem to which MOSFETs are subject due to the trench isolation structure has been controlled by combining taper angled trench etching and a rounded trench edge shape. A dual gate 0.4 µm nMOS/pMOS spacing has also been accomplished with no lateral gate dopant diffusion by an enlarged grain size tungsten polycide gate structure. These techniques can resolve the bottleneck problem of full CMOS SRAM cell size reduction, and realize a competitive cell size against conventional polysilicon resistor load SRAM cell (E/R type cell) or thin-film-transistor load SRAM cell (TFT type cell) structures. A test chip of a 256 k bit full CMOS SRAM was fabricated to verify the process integration of the shallow trench isolation with the retrograde shallow well design and the dual gate CMOS structure. It has been recognized that the above techniques are possible solutions for deep sub-micron high density full CMOS SRAM cell structure.

A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.