This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10 nm, the gate length is 20 nm, and the oxide thickness is 1 nm, the SGT shows a subthreshold swing of 63 mV/dec and a DIBL of -17 mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71 mV/dec and 77 mV/dec, respectively, and a DIBL of -47 mV and -75 mV, respectively. By adjusting the value of the gate work function, we define the off current at VG = 0 V and VD = 1 V. When the off current is set at 1 pA/µm, the SGT can realize a high on current of 1020 µA/µm at VG = 1 V and VD = 1 V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.

This paper describes the superior performances of the NAND EEPROM. Those are 1) a very small cell area: 4.83 µm2 using 0.7 µm design rule, 2) small block size for erasing: 4 Kbyte block erasing for 4 M-bit NAND EEPROM, 3) high speed programming: 180 nsec per byte for 4 M-bit NAND EEPROM, 4) large number of erase/program endurance cycles: more than 105 cycles for 4 M-bit NAND EEPROM. These extended performances coincide with the requirement for the EEPROM to replace magnetic memories such as hard and floppy disks. Especially, it is shown that NAND EEPROM has the capability to enlarge the erase/program endurance up to 3.6108 cycles. This endurance is a result of the erase and program mechanism of the NAND EEPROM cell. Fowler-Nordheim (F-N) tunneling currents flow from the substrate to the floating gate during programming and opposite currents flow during erasing. This bi-polarity F-N tunneling erase/program operation extends the life time of the tunnel oxide which results in an improved endurance.

This paper analyzes program and erase mechanisms for Floating Channel type Surrounding Gate Transistor (FC-SGT) Flash memory cells for the first time. In FC-SGT Flash memory cell, control gate, floating gate, drain and source is arranged vertically on the substrate. The body region is isolated from the substrate by the bottom source region. The cell is programmed by applying a high positive voltage to the control gate electrode with drain and source electrodes grounded. Erasing is performed by applying a high positive voltage to the drain and source electrodes with the control gate electrode grounded. The physical models for program and erase operations in FC-SGT Flash memory cell are developed. Program and erase operations based on the developed physical models are simulated by utilizing a device simulator. Program and erase characteristics obtained from the device simulation agree well with the results of analytical models. The FC-SGT Flash memory cell can realize program and erase operation with a floating body structure.

The data retention characteristics for Flash EEPROM degrade after a large number of write and erase cycles due to the increase of the tunnel oxide leakage current. This paper proposes a new write/erase method which uses a reverse polarity pulse after each erase pulse. By using this method, the leakage current can be suppressed. As a result, the read disturb time after 105cycles write/erase operation is more than 10 times longer in comparison with that of the conventional method. Moreover, using this method, the endurance cycle dependence of the threshold voltage after write and erase operation is also drastically improved.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

This paper describes the new write/erase operation methods in order to improve the read disturb characteristics for Flash EEPROM cells which are written by channel hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new operation methods is either applying a reverse polarity pulse after each erase pulse or applying a series of shorter erase pulses instead of a long single erase pulse. It is confirmed that by using the above operation methods, the leakage current can be suppressed, and then the read disturb life time after 105 cycles write/erase operation is more than 10 times longer in comparison with the conventional method. This memory cell by using the proposed write/erase operation method has superior potential for application to 256 Mbit Flash memories as beyond.

Recent technical trends of electrically programmable ROM (E-PROM) and electrically erasable and programmable PROM (EE-PROM) are reviewed in this paper. The reduction of the cell size and high speed access have been realized by the several breakthroughs of the device structure. The invention of the Flash EE-PROM makes the cell size same as that of E-PROM. Therefore, the bit capacity of Flash EE-PROM is supposed to be quadrupled every three years, same as DRAM's and E-PROM's scaling speed. Furthermore, the much higher density EE-PROM can be realized by the use of the NAND EE-PROM, recently. The invention of the NAND EE-PROM has enabled the semiconductor device engineers to replace the magnetic memory with Si device in very near future.

This paper describes a new reduction mechanism of the stress induced leakage current that is induced by step tunneling of electrons through the step tunneling sites. The concept of this mechanism is based on the deactivation of step tunneling sites for thin oxide. It is verified that the deactivation is electrically realized by the injected electrons int the sites. It is because the step tunneling probability of electrons though the deactivated sites is suppressed, since the electron capture cross section of the neutralized deactivation sites becomes extremely low. The deactivation scheme is as follows: (1) The deactivation of tunneling sites can be realized that the tunneling sites trapped holes change to neutralized tunneling sites due to electrons injection. (2) The injected electron can deactivate the activation tunneling sites only under energy level than the energy level of the injected electrons. It is shown that the above reduction phenomenon can be quantifiably with formulation. These results are very important for high reliable thin oxide films and for high performance ULSI.

This paper describes the analysis of the Stacked-Surrounding Gate Transistor (S-SGT) DRAM for the high speed and low voltage operation. The S-SGT DRAM is based on the new three dimensional (3D)-building memory array technology. In terms of the bit-lines signal voltage for read operation, it is found that the signal voltage of the S-SGT DRAM is larger than that of the conventional planar DRAM, the NAND-structured DRAM, and the SGT DRAM. The signal voltage of the S-SGT DRAM was found to depend on the pillar radius, the distance between the bit-line and the substrate, and the number of cells connected to one bit-line in comparison with the above three kinds of conventional DRAMs. Especially, with reducing the pillar radius (R), the signal voltage of the S-SGT DRAM becomes larger. In the concrete, in case that R is 0. 25 µm, the signal voltage of the S-SGT DRAM is about 160%, 160% and 120% in comparison with the planar DRAM, the SGT DRAM and the NAND-structured DRAM, respectively. Therefore, the S-SGT DRAM can realize larger S/N ratio. This advantage can realize the high speed and low voltage operation. Moreover, in case that the signal voltage is constant (0.15 V), the maximum number of cells connected to one bit-line for the S-SGT DRAM is about 2 times in comparison with the planar DRAM. This advantage makes it possible to reduce the number of both sense amplifiers and bit-lines. This is very suitable for reducing the total chip size of the S-SGT DRAM. Above all, it was found that the S-SGT DRAM is one of candidates for the high speed and low voltage operation DRAM in the future.

This paper describes the new α-particle induced soft error mechanism, the Minority Carrier Outflow (MCO) effect, which may seriously affect the reliability of the scaled DRAMs with three dimensional capacitors. The MCO chargge increases as the device size miniaturizes because of the three dimensional capacitor effect as below. As the device scales down, the storage node volume decreases which results in the higher minority carrier density in the storage node and larger outflow charge. Also as the device plan view miniaturizes, the stack capacitor height or trench depth does not scales down or even increases to keep the storage node capacitance, therefore the initially generated minority carrier becomes larger. A simple analytical MCO model is introduced to evaluate the MCO effect quantitatively. The model agrees well with the three dimensional device simulation. The MCO model predicts that the life time of the minority carrier in the storage node strongly affects the MCO charge, however, even when the life time is as small as the order of 100 ps, the MCO effect can be the major soft error mechanism.

The data retention characteristics of a Flash memory cell with a self-aligned double poly-Si stacked structure have been drastically improved by applying a bi-polarity write and erase technology which uses uniform Fowler-Nordheim tunneling over the whole channel area both during write and erase. It is clarified experimentally that the detrapping of electrons from the gate oxide to the substrate results in an extended retention time. A bi-polarity write and erase technology also guarantees a wide cell threshold voltage window even after 106 write/erase cycles. This technology results in a highly reliable EEPROM with an extended data retention time.

This paper presents the history of Flash memories and the basic concept of their functions and also reviews a variety of Flash EEPROM's so far. As Flash memories have two influential features, non-volatility and low cost per bit, they are expected to become a driving force after DRAM's to support the semiconductor industry for the next thirty years, replacing hard and floppy disks which have a large market.

This paper describes the evaluation of the Voltage Down Converter (VDC) with low ratio of consuming current to load current in DC/AC operation mode. The stability, response and power consumption are investigated. First, for the stability and response, the VDC can operate in the condition that the bounce of the down voltage (dVDL) is no more than 10% of the setting voltage and the maximum load operation frequency (fmax) is 100 MHz at the average load current 70 mA (the maximum load current 140 mA). Secondly, for the power consumption, by using this VDC technology, the value of IC/IL can be suppressed to 5.1E-4 (IC: total consuming current in VDC, IL: average load current) in the condition that dVDL is no more than 10% of the setting voltage and fmax is 10 MHz at the average load current 70 mA. Thus, it is made clear that the VDC can realize high stability, good response and low power consumption at the same time. This technology is suitable for high performance ULSIs which require large load current and low-power consumption.

A high performance voltage down converter (VDC) is proposed in this paper. The proposed VDC can automatically control the driving current in seven phases to reduce the fluctuation of output voltage in VDC. By using above new flexible control technology of driving current, the fluctuation of output voltage can be suppressed to less than 10% and the average consuming current of VDC can be suppressed to 34 µA, even if the operation frequency is 200 MHz at the average driving current 100 mA. Therefore, the proposed VDC can operate with large driving current, low-power consumption and good response at the same time. Above all, this technology is very suitable for high perform ULSIs which require large load current, very low-power and high speed operation.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.