This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10 nm, the gate length is 20 nm, and the oxide thickness is 1 nm, the SGT shows a subthreshold swing of 63 mV/dec and a DIBL of -17 mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71 mV/dec and 77 mV/dec, respectively, and a DIBL of -47 mV and -75 mV, respectively. By adjusting the value of the gate work function, we define the off current at VG = 0 V and VD = 1 V. When the off current is set at 1 pA/µm, the SGT can realize a high on current of 1020 µA/µm at VG = 1 V and VD = 1 V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.

This paper analyzes program and erase mechanisms for Floating Channel type Surrounding Gate Transistor (FC-SGT) Flash memory cells for the first time. In FC-SGT Flash memory cell, control gate, floating gate, drain and source is arranged vertically on the substrate. The body region is isolated from the substrate by the bottom source region. The cell is programmed by applying a high positive voltage to the control gate electrode with drain and source electrodes grounded. Erasing is performed by applying a high positive voltage to the drain and source electrodes with the control gate electrode grounded. The physical models for program and erase operations in FC-SGT Flash memory cell are developed. Program and erase operations based on the developed physical models are simulated by utilizing a device simulator. Program and erase characteristics obtained from the device simulation agree well with the results of analytical models. The FC-SGT Flash memory cell can realize program and erase operation with a floating body structure.

This paper describes the analysis of the Stacked-Surrounding Gate Transistor (S-SGT) DRAM for the high speed and low voltage operation. The S-SGT DRAM is based on the new three dimensional (3D)-building memory array technology. In terms of the bit-lines signal voltage for read operation, it is found that the signal voltage of the S-SGT DRAM is larger than that of the conventional planar DRAM, the NAND-structured DRAM, and the SGT DRAM. The signal voltage of the S-SGT DRAM was found to depend on the pillar radius, the distance between the bit-line and the substrate, and the number of cells connected to one bit-line in comparison with the above three kinds of conventional DRAMs. Especially, with reducing the pillar radius (R), the signal voltage of the S-SGT DRAM becomes larger. In the concrete, in case that R is 0. 25 µm, the signal voltage of the S-SGT DRAM is about 160%, 160% and 120% in comparison with the planar DRAM, the SGT DRAM and the NAND-structured DRAM, respectively. Therefore, the S-SGT DRAM can realize larger S/N ratio. This advantage can realize the high speed and low voltage operation. Moreover, in case that the signal voltage is constant (0.15 V), the maximum number of cells connected to one bit-line for the S-SGT DRAM is about 2 times in comparison with the planar DRAM. This advantage makes it possible to reduce the number of both sense amplifiers and bit-lines. This is very suitable for reducing the total chip size of the S-SGT DRAM. Above all, it was found that the S-SGT DRAM is one of candidates for the high speed and low voltage operation DRAM in the future.