An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)

Tetsuo ENDOH; Tairiku NAKAMURA; Fujio MASUOKA

An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)

Tetsuo ENDOH, Tairiku NAKAMURA, Fujio MASUOKA

Full Text Views

0

Cite this

Summary :

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.7 pp.905-910

Publication Date: 1997/07/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)

Category: Novel Structure Devices

Cite this

Copy

Tetsuo ENDOH, Tairiku NAKAMURA, Fujio MASUOKA, "An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 7, pp. 905-910, July 1997, doi: .
Abstract: A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_7_905/_p

Copy

@ARTICLE{e80-c_7_905,
author={Tetsuo ENDOH, Tairiku NAKAMURA, Fujio MASUOKA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)},
year={1997},
volume={E80-C},
number={7},
pages={905-910},
abstract={A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.},
keywords={},
doi={},
ISSN={},
month={July},}

Copy

TY - JOUR
TI - An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT)
T2 - IEICE TRANSACTIONS on Electronics
SP - 905
EP - 910
AU - Tetsuo ENDOH
AU - Tairiku NAKAMURA
AU - Fujio MASUOKA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1997
AB - A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.
ER -