With increasing technology scaling and the use of lower voltages, more research interest is being shown in variability-tolerant analog front end design. In this paper, we describe an adaptive amplitude control transmitter that is operated using differential signaling to reduce the temperature variability effect. It enables low power, low voltage operation by synergy between adaptive amplitude control and Vth temperature variation control. It is suitable for high-speed interface applications, particularly cable interfaces. By installing an aggressor circuit to estimate transmitter jitter and changing its frequency and activation rate, we were able to analyze the effects of the interface block on the input buffer and thence on the entire system. We also report a detailed estimation of the receiver clock-data recovery (CDR) operation for transmitter jitter estimation. These investigations provide suggestions for widening the eye opening of the transmitter.

We report the control of threshold voltage (Vth) for low voltage (5V) operation in OFET by using double gate dielectric layers composed of poly (vinyl cinnamate) and SiO2. We succeeded in realizing a driving voltage of -5V and Vth shift by c.a. 1.0V. And programmed Vth was almost unchanged for 104s, where the relative change of Vth remains more than 99%.

The threshold voltage variations for actual size MOSFETs obtained by capacitance measurement are compared with those obtained by the current measurement, and their differences are studied for the first time. It is found that the threshold voltage variations obtained by the capacitance measurement show the similar behavior to those current measurement and the absolute value is less than those obtained by the current measurement. The reason for the difference is partially explained by that the local channel dopant non-uniformity along the current path makes the threshold voltage variation obtained from current measurement larger. It is found that the flat-band voltage variations, which are obtained from the measured C-V curves, are small and not significant to the threshold voltage variation.

In this paper, an analytical threshold voltage model of the strained gate-all-around MOSFET fabricated on the Si1-xGex virtual substrate is presented by solving the two-dimensional Poisson equation. The impact of key parameters such as the strain, channel length, gate oxide thickness and radius of the silicon cylinder on the threshold voltage has been investigated. It has been demonstrated that the threshold voltage decreases as the strain in the channel increases. The threshold voltage roll-off becomes severe when increasing the Ge content in the Si1-xGex virtual substrate. The model is found to tally well with the device simulator.

The effect of annealing on the field emission characteristics of a field emitter comprising diamond micropowder was investigated. The threshold voltage Vth at which the emission current begins to flow decreased as the annealing temperature increased, and a minimum Vth was obtained at an annealing temperature of 1345K. The reduction in threshold voltage was due to a reduction in the work function with annealing.

We have demonstrated tunable extit{n}-channel fullerene and extit{p}-channel pentacene OFETs and CMOS inverter circuit based on a bilayer-dielectric structure of CYTOP (poly(perfluoroalkenyl vinyl ether)) electret and SiO$_{2}$. For both OFET types, the $V_{mathrm{th}}$ can be electrically tuned thanks to the charge-trapping at the interface of CYTOP and SiO$_{2}$. The stability of the shifted $V_{mathrm{th}}$ was investigated through monitoring a change in transistor current. The measured transistor current versus time after programming fitted very well with a stretched-exponential distribution with a long time constant up to 10$^{6}$ s. For organic CMOS inverter, after applying the program gate voltages for extit{n}-channel fullerene or extit{p}-channel pentacene elements, the voltage transfer characteristics were shifted toward more positive values, resulting in a modulation of the noise margin. We realized that at a program gate voltage of 60,V for extit{p}-channel OFET, the circuit switched at 4, 8,V, that is close to half supply voltage $V_{mathrm{DD}}$, leading to the maximum electrical noise immunity of the inverter circuit.

We have studied photo-induced effects in a p-type transistor based on a [1]benzothieno[3,2-b]benzothiophene (BTBT) derivative. Repetition of blue light irradiation and electrical characterization under dark reveals that its threshold voltage gradually shifts in the positive direction as the cumulative exposure time increases. This shift is slowly reversed when the transistor is stored under dark. The onset voltage defined as the gate bias at which the sub-threshold current exceeds a certain level behaves in a similar manner. Mobility remains more or less the same during this exposure period and the storage period. Time evolution of the threshold voltage shift is fit by a model assuming two charged meta-stable states decaying independently. A set of parameters consists of a decay constant for each state and the ratio of the two states. A single parameter set reproduces the positive shift during the exposure period and the negative shift during the storage period. Time evolution of the onset voltage is reproduced by the same parameter set. We have also studied photo-induced effects in two types of n-type transistors where either a pure solution of a perylene derivative or a solution mixed with an insulating polymer is used for printing each semiconductor layer. A similar behavior is observed for these transistors: blue light irradiation under a negative gate bias shifts the threshold and the onset voltages in the negative direction and these shifts are reversed under dark. The two-component model reproduces the behavior of these voltage shifts and the parameter set is slightly different among the two transistors made from different semiconductor solutions. The onset voltage shift is well correlated to the threshold voltage shift for the three types of organic transistors studied here. The onset voltage is more sensitive to illumination than the threshold voltage and its sensitivity differs among transistors.

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-Vt technology, as compared to that of the classic double-edge-triggered flip-flop design.

Distribution of current onset voltage (COV) as well as threshold voltage (VTH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65 nm technology is statistically analyzed. Although VTH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET by channel doping because most of TFETs are fabricated on SOI substrates. In this paper, we propose a technique to control VT of the TFET by putting an additional VT-control doping region (VDR) between source and channel. We examine how much VT is changed by doping concentration of VDR. The change of doping concentration modulates VT because it changes the semiconductor work function difference, ψs,channel-ψs,source, at off-state. Also, the effect of the size of VDR is investigated. The region can be confined to the silicon surface because most of tunneling occurs at the surface. At the same time, we study the optimum width of this region while considering the mobility degradation by doping. Finally, the effect of the SOI thickness on the VDR adjusted VT of TFET is also investigated.

A gated sense amplifier (GSA) consisting of a low-Vt gated preamplifier (LGA) and a high-Vt sense amplifier (SA) is proposed. The gating scheme of the LGA enables quick amplification of an initial cell signal voltage (vS0) because of its low Vt and prevents the cell signal from degrading due to interference noise between data lines. As for a conventional sense amplifier (CSA), this new type of noise causes sensing error, and the noise-generation mechanism was clarified for the first time by analysis of vS0. The high-Vt SA holds the amplified signal and keeps subthreshold current low. Moreover, the gating scheme of the low-Vt MOSFETs in the LGA drives the I/O line quickly. The GSA thus simultaneously achieves fast sensing, low-leakage data holding, and fast I/O driving, even for sub-1-V mid-point sensing. The GSA is promising for future sub-1-V gigabit dynamic random-access memory (DRAM) because of reduced variations in the threshold voltage of MOSFETs; thus, the offset voltage of the LGA is reduced. The effectiveness of the GSA was verified with a 70-nm 512-Mbit DRAM chip. It demonstrated row access time (tRCD) of 16.4 ns and read access (tAA) of 14.3 ns at array voltage of 0.9 V.

In this paper, a theoretical analysis of current-controlled (CC-) MOS current mode logic (MCML) is reported. Furthermore, the circuit performance of the CC-MCML with the auto-detection of threshold voltage (Vth) fluctuation is evaluated. The proposed CC-MCML with the auto-detection of Vth fluctuation automatically suppresses the degradation of circuit performance induced by the Vth fluctuations of the transistors automatically, by detecting these fluctuations. When a Vth fluctuation of ± 0.1 V occurs on the circuit, the cutoff frequency of the circuit is increased from 0 Hz to 3.5 GHz by using the proposed CC-MCML with the auto-detection of Vth fluctuation.

An on-chip temperature compensation active bias circuit having tunable temperature slope has been proposed, and its application to an X-band GaAs FET monolithic microwave integrated circuit (MMIC) power amplifier (PA) is described. The proposed bias circuit can adjust the temperature slope of gate voltage according to the bias condition of the PA, and also realizes the higher temperature slope of the gate voltage by employing the diode and the FET which operates at near threshold voltage (Vt) in the bias circuit. As a result, the gain of PAs operated at any bias conditions is kept almost constant against temperature by applying the proposed bias circuit. Moreover, the proposed bias circuit can be integrated in the same chip with the MMIC PA since it does not need off-chip components, and operates with only negative voltage source. The fabricated results of the on-chip temperature compensation active bias circuit shows that the temperature slope of the gate voltage varies from 2.1 to 6.3 mV/, which is enough to compensate the gain of not only class-B PA but also class-A PA. The gain deviation of the developed GaAs FET MMIC PA with the proposed bias circuit has been reduced from 3.3 dB to 0.6 dB in the temperature range of 100.

We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 µm and L = 0.18 µm in a 1616 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 to 75. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput.

Effects of stress in passivation films on the electrical properties of (0001) AlGaN/GaN HEMTs are numerically analysed in the framework of the edge force model with anisotropical characteristics in elastic properties of group-III nitrides explicitly considered. Practical compressive stresses in passivation films induce negative piezoelectric charges below the gates and bring forth a-few-volt shallower threshold voltages. In addition, the shift in the threshold voltage due to the compressive stress is proportional to LG-1.1-1.5 with gate length LG, which is comparable to the expectation based on the charge balance scheme. These result suggest that passivation films with designed stress might play a crucial role in realising AlGaN/GaN HEMTs with shallow or positive threshold voltages.

An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.

Design of the 30 nm FinFETs and Double Gate MOSFETs with the halo structure for suppressing the threshold voltage roll-off and improving the subthreshold swing at the same time is proposed for the first time. The performances of nano scale FinFETs and Double Gate MOSFETs with the halo structure are analyzed using a two-dimensional device simulator. The device characteristics, focusing especially on the threshold voltage and subthreshold slope, are investigated for the different gate length, body thickness, and halo impurity concentration. From the viewpoint of body potential control, it is made clear on how to design the halo structure to suppress the short channel effects and improve the subthreshold-slope. It is shown that by introducing the halo structure to FinFETs and Double Gate MOSFETs, nano-scale FinFETs and Double Gate MOSFETs achieve an improved S-factor and suppressed threshold voltage Vth roll-off simultaneously.

The control of the organic field-effect transistor characteristics is necessary to produce the integrated circuits using organic semiconductors. Variations in the poly (3-hexylthiophene) field-effect transistor characteristics upon post-treatment such as thermal treatment and voltage treatment in N2 atmosphere have been investigated. The controllability and reproducibility of the threshold voltage and mobility were achieved as a result of the post-treatments.

This paper describes a new design concept, the Body Bias Voltage Set (BBVS), and presents the effect of the BBVS on static power, operating speed, and area overhead in an FPGA with field-programmable Vth components. A Flex Power FPGA is an FPGA architecture to solve the static power problem by the fine grain field-programmable Vth control method. Since the Vth of transistors for specific circuit blocks in the Flex Power FPGA is chosen from a set of Vth values defined by a BBVS, selection of a particular BBVS is an important design decision. A particular BBVS is chosen by selecting body biases from among several supplied body bias candidates. To select the optimal BBVS, we provide 136 BBVSs and perform a thorough search. In a BBVS of less Vth steps, the deepest reverse body bias for high-Vth transistors does not necessarily result in optimal conditions. A BBVS of 0.0 V and -0.8 V, which requires 1.65 times the original area, utilizes as little as 1/30 of the static power of a conventional FPGA without performance degradation. Use of an aggressive forward body bias voltage such as +0.6 V for lowest-Vth, performance is increased by up to 10%. Another BBVS of +0.6 V, 0.0 V, and -0.8 V reduces static power to 14.06% while maintaining a 10% performance increase, but it requires 2.75-fold area.