We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 MΩ by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-µm 2P-4M CMOS process technology is described. The resistance was 13 MΩ for a tail current of 10 nA and 135 MΩ for 1 nA. The chip area was 105 µm110 µm. Our resistor circuit is useful to construct many high-resistance resistors in a small chip area.

A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.

We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9 dB compared with that of the uncoupled network as a result of noise shaping.

We present on-chip oscillator arrays synchronized by random noises, aiming at skew-free clock distribution on synchronous digital systems. Nakao et al. recently reported that independent neural oscillators can be synchronized by applying temporal random impulses to the oscillators [1],[2]. We regard neural oscillators as independent clock sources on LSIs; i.e., clock sources are distributed on LSIs, and they are forced to synchronize through the use of random noises. We designed neuron-based clock generators operating at sub-RF region (< 1 GHz) by modifying the original neuron model to a new model that is suitable for CMOS implementation with 0.25-µm CMOS parameters. Through circuit simulations, we demonstrate that i) the clock generators are certainly synchronized by pseudo-random noises and ii) clock generators exhibited phase-locked oscillations even if they had small device mismatches.

We developed a CMOS watchdog sensor that simulates the changes in quality of perishables such as farm and marine products. The sensor can imitate a chemical reaction that causes the changes in the quality of perishables, with a wide range of activation energy from 0.1 eV to 0.7 eV. Attached to perishable goods, the sensor simulates the deterioration of the goods caused by surrounding temperatures. By reading the output of the sensor, consumers can determine whether the goods are fresh or not. This sensor consists of subthreshold CMOS circuits with a low-power consumption of 5 µW or less.

The Belousov-Zhabotinsky (BZ) reaction provides us important clues in controlling 2D phase-lagged stable synchronous patterns in an excitable medium. Because of the difficulty in computing reaction-diffusion systems in large systems using conventional digital processors, we here propose a cellular-automaton (CA) circuit that emulates the BZ reaction. In the circuit, a two-dimensional array of parallel processing cells is responsible for fast emulation, and its operation rate is independent of the system size. The operations of the proposed CA circuit were demonstrated by using a simulation program with integrated circuit emphasis (SPICE).

We found a new class of stochastic resonance (SR) in a simple neural network that consists of i) photoreceptors generating nonuniform outputs for common inputs with random offsets, ii) an ensemble of noisy McCulloch-Pitts (MP) neurons each of which has random threshold values in the temporal domain, iii) local coupling connections between the photoreceptors and the MP neurons with variable receptive fields (RFs), iv) output cells, and v) local coupling connections between the MP neurons and the output cells. We calculated correlation values between the inputs and the outputs as a function of the RF size and intensities of the random components in photoreceptors and the MP neurons. We show the existence of "optimal noise intensities" of the MP neurons under the nonidentical photoreceptors and "nonzero optimal RF sizes," which indicated that optimal correlation values of this SR model were determined by two critical parameters; noise intensities (well-known) and RF sizes as a new parameter.

An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.

An ultralow power constant reference current circuit with low temperature dependence for micropower electronic applications is proposed in this paper. This circuit consists of a constant-current subcircuit and a bias-voltage subcircuits, and it compensates for the temperature characteristics of mobility µ, thermal voltage VT, and threshold voltage VTH in such a way that the reference current has small temperature dependence. A SPICE simulation demonstrated that reference current and total power dissipation is 97.7 nA, 1.1 µW, respectively, and the variation in the reference current can be kept very small within 4% in a temperature range from -20 to 100.

A voltage-controlled oscillator (VCO) tolerant to process variations at lower supply voltage was proposed. The circuit consists of an on-chip threshold-voltage-monitoring circuit, a current-source circuit, a body- biasing control circuit, and the delay cells of the VCO. Because variations in low-voltage VCO frequency are mainly determined by that of the current in delay cells, a current-compensation technique was adopted by using an on-chip threshold-voltage-monitoring circuit and body-biasing circuit techniques. Monte Carlo SPICE simulations demonstrated that variations in the oscillation frequency by using the proposed techniques were able to be suppressed about 65% at a 1-V supply voltage, compared to frequencies with and without the techniques.

Edge computing, which has been gaining attention in recent years, has many advantages, such as reducing the load on the cloud, not being affected by the communication environment, and providing excellent security. Therefore, many researchers have attempted to implement neural networks, which are representative of machine learning in edge computing. Neural networks can be divided into inference and learning parts; however, there has been little research on implementing the learning component in edge computing in contrast to the inference part. This is because learning requires more memory and computation than inference, easily exceeding the limit of resources available for edge computing. To overcome this problem, this research focuses on the optimizer, which is the heart of learning. In this paper, we introduce our new optimizer, hardware-oriented logarithmic momentum estimation (Holmes), which incorporates new perspectives not found in existing optimizers in terms of characteristics and strengths of hardware. The performance of Holmes was evaluated by comparing it with other optimizers with respect to learning progress and convergence speed. Important aspects of hardware implementation, such as memory and operation requirements are also discussed. The results show that Holmes is a good match for edge computing with relatively low resource requirements and fast learning convergence. Holmes will help create an era in which advanced machine learning can be realized on edge computing.

Deep neural network (NN) has been widely accepted for enabling various AI applications, however, the limitation of computational and memory resources is a major problem on mobile devices. Quantized NN with a reduced bit precision is an effective solution, which relaxes the resource requirements, but the accuracy degradation due to its numerical approximation is another problem. We propose a novel quantized NN model employing the “dithering” technique to improve the accuracy with the minimal additional hardware requirement at the view point of the hardware-algorithm co-designing. Dithering distributes the quantization error occurring at each pixel (neuron) spatially so that the total information loss of the plane would be minimized. The experiment we conducted using the software-based accuracy evaluation and FPGA-based hardware resource estimation proved the effectiveness and efficiency of the concept of an NN model with dithering.

An annealing processor based on the Ising model is a remarkable candidate for combinatorial optimization problems and it is superior to general von Neumann computers. CMOS-based implementations of the annealing processor are efficient and feasible based on current semiconductor technology. However, critical problems with annealing processors remain. There are few simulated spins and inflexibility in terms of implementable graph topology due to hardware constraints. A prior approach to overcoming these problems is to emulate a complicated graph on a simple and high-density spin array with so-called minor embedding, a spin duplication method based on graph theory. When a complicated graph is embedded on such hardware, numerous spins are consumed to represent high-degree spins by combining multiple low-degree spins. In addition to the number of spins, the quality of solutions decreases as a result of dummy strong connections between the duplicated spins. Thus, the approach cannot handle large-scale practical problems. This paper proposes a flexible and scalable hardware architecture with time-division multiplexing for massive spins and high-degree topologies. A target graph is separated and mapped onto multiple virtual planes, and each plane is subject to interleaved simulation with time-division processing. Therefore, the behavior of high-degree spins is efficiently emulated over time, so that no dummy strong connections are required, and the solution quality is accordingly improved. We implemented a prototype hardware design for FPGAs, and we evaluated the proposed method in a software-based annealing processor simulator. The results indicate that the method increased the spins that can be deployed. In addition, our time-division multiplexing architecture improved the solution quality and convergence time with reasonable resource consumption.

Neural networks (NNs) fail to perform well or make excessive predictions when predicting out-of-distribution or unseen datasets. In contrast, Bayesian neural networks (BNNs) can quantify the uncertainty of their inference to solve this problem. Nevertheless, BNNs have not been widely adopted owing to their increased memory and computational cost. In this study, we propose a novel approach to extend binary neural networks by introducing a probabilistic interpretation of binary weights, effectively converting them into BNNs. The proposed approach can reduce the number of weights by half compared to the conventional method. A comprehensive comparative analysis with established methods like Monte Carlo dropout and Bayes by backprop was performed to assess the performance and capabilities of our proposed technique in terms of accuracy and capturing uncertainty. Through this analysis, we aim to provide insights into the advantages of this Bayesian extension.