IEICE TRANSACTIONS on Fundamentals
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
Summary :
A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.2 pp.436-442
- Publication Date
- 2009/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E92.A.436
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
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Taichi OGAWA, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEMIYA, "Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 2, pp. 436-442, February 2009, doi: 10.1587/transfun.E92.A.436.
Abstract: A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.436/_p
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@ARTICLE{e92-a_2_436,
author={Taichi OGAWA, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEMIYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits},
year={2009},
volume={E92-A},
number={2},
pages={436-442},
abstract={A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.},
keywords={},
doi={10.1587/transfun.E92.A.436},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 436
EP - 442
AU - Taichi OGAWA
AU - Tetsuya HIROSE
AU - Tetsuya ASAI
AU - Yoshihito AMEMIYA
PY - 2009
DO - 10.1587/transfun.E92.A.436
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E92-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2009
AB - A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
ER -
English
