Stochastic Computing (SC) allows additions and multiplications to be realized with lower power than the conventional binary operations if we admit some errors. However, for many complex functions which cannot be realized by only additions and multiplications, we do not know a generic efficient method to calculate a function by using an SC circuit; it is necessary to realize an SC circuit by using a generic method such as polynomial approximation methods for such a function, which may lose the advantage of SC. Thus, there have been many researches to consider efficient SC realization for specific functions; an efficient SC square root circuit with a feedback circuit was proposed by D. Wu et al. recently. This paper generalizes the SC square root circuit with a feedback circuit; we identify a situation when we can implement a function efficiently by an SC circuit with a feedback circuit. As examples of our generalization, we propose SC circuits to calculate the n-th root calculation and division. We also show our analysis on the accuracy of our SC circuits and the hardware costs; our results show the effectiveness of our method compared to the conventional SC designs; our framework may be able to implement a SC circuit that is better than the existing methods in terms of the hardware cost or the calculation error.

An efficient optical power splitter constructed by a metal-dielectric-metal plasmonic waveguide with a resonator structure has been analyzed. The method of solution is the finite difference time domain (FD-TD) method with the piecewise linear recursive convolution (PLRC) method. The resonator structure consists of input/output waveguides and a narrow waveguide with a T-junction. The power splitter with the resonator structure is expressed by an equivalent transmission-line circuit. We can find that the transmittance and reflectance calculated by the FD-TD method and the equivalent circuit are matched when the difference in width between the input/output waveguides and the narrow waveguide is small. It is also shown that the transmission wavelength can be adjusted by changing the narrow waveguide lengths that satisfy the impedance matching condition in the equivalent circuit.

A 150 GHz fundamental oscillator employing an inter-stage matching network based on a transmission line is presented in this letter. The proposed oscillator consists of a two-stage common-emitter amplifier loop, whose inter-stage connections are optimized to meet the oscillation condition. The oscillator is designed in a 130-nm SiGe BiCMOS process that offers fT and fMAX of 350 GHz and 450 GHz. According to simulation results, an output power of 3.17 dBm is achieved at 147.6 GHz with phase noise of -115 dBc/Hz at 10 MHz offset and figure-of-merit (FoM) of -180 dBc/Hz.

A wireless sensor terminal module of 5cc size (2.5 cm × 2.5 cm × 0.8 cm) that does not require a battery is proposed by integrating three kinds of circuit technologies. (i) a low-power sensor interface: an FM modulation type CMOS sensor interface circuit that can operate with a typical power consumption of 24.5 μW was fabricated by the 0.7-μm CMOS process technology. (ii) power supply to the sensor interface circuit: a wireless power transmission characteristic to a small-sized PCB spiral coil antenna was clarified and applied to the module. (iii) wireless sensing from the module: backscatter communication technology that modulates the signal from the base terminal equipment with sensor information and reflects it, which is used for the low-power sensing operation. The module fabricated includes a rectifier circuit with the PCB spiral coil antenna that receives wireless power transmitted from base terminal equipment by electromagnetic resonance coupling and converts it into DC power and a sensor interface circuit that operates using the power. The interface circuit modulates the received signal with the sensor information and reflects it back to the base terminal. The module could achieve 100 mm communication distance when 0.4 mW power is feeding to the sensor terminal.

L-type LC/CL matching circuits are well known for their simple analytical solutions and have been applied to many radio-frequency (RF) circuits. When actually constructing a circuit, parasitic elements are added to inductors and capacitors. Therefore, each L and C element has a self-resonant frequency, which affects the characteristics of the matching circuit. In this paper, the parallel parasitic capacitance to the inductor and the series parasitic inductor to the capacitance are taken up as parasitic elements, and the details of the effects of the self-resonant frequency of each element on the S11, voltage standing wave ratio (VSWR) and S21 characteristics are reported. When a parasitic element is added, each characteristic basically tends to deteriorate as the self-resonant frequency decreases. However, as an interesting feature, we found that the combination of resonant frequencies determines the VSWR and passband characteristics, regardless of whether it is the inductor or the capacitor.

Wide deployment of artificial intelligence (AI) is inducing exponentially growing energy consumption. Traditional digital platforms are becoming difficult to fulfill such ever-growing demands on energy efficiency as well as computing latency, which necessitates the development of high efficiency analog hardware platforms for AI. Recently, optical and electrooptic hybrid computing is reactivated as a promising analog hardware alternative because it can accelerate the information processing in an energy-efficient way. Integrated photonic circuits offer such an analog hardware solution for implementing photonic AI and machine learning. For this purpose, we proposed a photonic analog of support vector machine and experimentally demonstrated low-latency and low-energy classification computing, which evidences the latency and energy advantages of optical analog computing over traditional digital computing. We also proposed an electrooptic Hopfield network for classifying and recognizing time-series data. This paper will review our work on implementing classification computing and Hopfield network by leveraging silicon photonic circuits.

This article reviews the author’s group research achievements in analog/mixed-signal circuit and system area with introduction of how they came up with the ideas. Analog/mixed-signal circuits and systems have to be designed as well-balanced in many aspects, and coming up ideas needs some experiences and discussions with researchers. It is also heavily dependent on researchers. Here, the author’s group own experiences are presented as well as their research motivations.

A method for bandwidth enhancement of radar cross section (RCS) reduction by metasurfaces was studied. Scattering cancellation is one of common methods for reducing RCS of target scatterers. It occurs when the wave scattered by the target scatterer and the wave scattered by the canceling scatterer are the same amplitude and opposite phase. Since bandwidth of scattering cancellation is usually narrow, we proposed the bandwidth enhancement method using metasurfaces, which can control the frequency dependence of the scattering phase. We designed and fabricated a metasurface composed of a patch array on a grounded dielectric substrate. Numerical and experimental evaluations confirmed that the metasurface enhances the bandwidth of 10dB RCS reduction by 52% bandwidth ratio of the metasurface from 34% bandwidth ratio of metallic cancelling scatterers.

Logic circuits based on a photonic integrated circuit (PIC) have attracted significant interest due to their ultra-high-speed operation. However, they have a fundamental disadvantage that a large amount of the optical signal power is discarded in the path from the optical source to the optical output, which results in significant power consumption. This optical signal power loss is called a garbage output. To address this issue, this paper considers a circuit design without garbage outputs. Although a method for synthesizing an optical logic circuit without garbage outputs is proposed, this synthesis method can not obtain the optimal solution, such as a circuit with the minimum number of gates. This paper proposes a cross-bar gate logic (CBGL) as a new logic structure for optical logic circuits without garbage outputs, moreover enumerates the CBGLs with the minimum number of gates for all three input logic functions by an exhaustive search. Since the search space is vast, our enumeration algorithm incorporates a technique to prune it efficiently. Experimental results for all three-input logic functions demonstrate that the maximum number of gates required to implement the target function is five. In the best case, the number of gates in enumerated CBGLs is one-half compared to the existing method for optical logic circuits without garbage outputs.

Stabilizer-based quantum secret sharing has two methods to reconstruct a quantum secret: The erasure correcting procedure and the unitary procedure. It is known that the unitary procedure has a smaller circuit width. On the other hand, it is unknown which method has smaller depth and fewer circuit gates. In this letter, it is shown that the unitary procedure has smaller depth and fewer circuit gates than the erasure correcting procedure which follows a standard framework performing measurements and unitary operators according to the measurements outcomes, when the circuits are designed for quantum secret sharing using the [[5, 1, 3]] binary stabilizer code. The evaluation can be reversed if one discovers a better circuit for the erasure correcting procedure which does not follow the standard framework.

As more and more programs handle personal information, the demand for secure handling of data is increasing. The protocol that satisfies this demand is called Secure function evaluation (SFE) and has attracted much attention from a privacy protection perspective. In two-party SFE, two mutually untrustworthy parties compute an arbitrary function on their respective secret inputs without disclosing any information other than the output of the function. For example, it is possible to execute a program while protecting private information, such as genomic information. The garbled circuit (GC) — a method of program obfuscation in which the program is divided into gates and the output is calculated using a symmetric key cipher for each gate — is an efficient method for this purpose. However, GC is computationally expensive and has a significant overhead even with an accelerator. We focus on hardware acceleration because of the nature of GC, which is limited to certain types of calculations, such as encryption and XOR. In this paper, we propose an architecture that accelerates garbling by running multiple garbling engines simultaneously based on the latest FPGA-based GC accelerator. In this architecture, managers are introduced to perform multiple rows of pipeline processing simultaneously. We also propose an optimized implementation of RAM for this FPGA accelerator. As a result, it achieves an average performance improvement of 26% in garbling the same set of programs, compared to the state-of-the-art (SOTA) garbling accelerator.

Most quantum circuits require SWAP gate insertion to run on quantum hardware with limited qubit connectivity. A promising SWAP gate insertion method for blocks of commuting two-qubit gates is a predetermined swap strategy which applies layers of SWAP gates simultaneously executable on the coupling map. A good initial mapping for the swap strategy reduces the number of required swap gates. However, even when a circuit consists of commuting gates, e.g., as in the Quantum Approximate Optimization Algorithm (QAOA) or trotterized simulations of Ising Hamiltonians, finding a good initial mapping is a hard problem. We present a SAT-based approach to find good initial mappings for circuits with commuting gates transpiled to the hardware with swap strategies. Our method achieves a 65% reduction in gate count for random three-regular graphs with 500 nodes. In addition, we present a heuristic approach that combines the SAT formulation with a clustering algorithm to reduce large problems to a manageable size. This approach reduces the number of swap layers by 25% compared to both a trivial and random initial mapping for a random three-regular graph with 1000 nodes. Good initial mappings will therefore enable the study of quantum algorithms, such as QAOA and Ising Hamiltonian simulation applied to sparse problems, on noisy quantum hardware with several hundreds of qubits.

This paper presents a compact fully-differential distributed amplifier using a coupled inductor. Differential distributed amplifiers are widely required in optical communication systems. Most of the distributed amplifiers reported in the past are single-ended or pseudo-differential topologies. In addition, the differential distributed amplifiers require many inductors, which increases the silicon cost. In this study, we use differentially coupled inductors to reduce the chip area to less than half and eliminate the difficulties in layout design. The challenge in using coupled inductors is the capacitive parasitic coupling that degrades the flatness of frequency response. To address this challenge, the odd-mode image parameters of a differential artificial transmission line are derived using a simple loss-less model. Based on the analytical results, we optimize the dimensions of the inductor with the gradient descent algorithm to achieve accurate impedance matching and phase matching. The amplifier was fabricated in 0.18-µm CMOS technology. The core area of the amplifier is 0.27 mm2, which is 57% smaller than the previous work. Besides, we demonstrated a small group delay variation of ±2.7 ps thanks to the optimization. the amplifier successfully performed 30-Gbps NRZ and PAM4 transmissions with superior jitter performance. The proposed technique will promote the high-density integration of differential traveling wave devices.

The Variational Quantum Eigensolver (VQE) algorithm is gaining interest for its potential use in near-term quantum devices. In the VQE algorithm, parameterized quantum circuits (PQCs) are employed to prepare quantum states, which are then utilized to compute the expectation value of a given Hamiltonian. Designing efficient PQCs is crucial for improving convergence speed. In this study, we introduce problem-specific PQCs tailored for optimization problems by dynamically generating PQCs that incorporate problem constraints. This approach reduces a search space by focusing on unitary transformations that benefit the VQE algorithm, and accelerate convergence. Our experimental results demonstrate that the convergence speed of our proposed PQCs outperforms state-of-the-art PQCs, highlighting the potential of problem-specific PQCs in optimization problems.

This paper analyzes the typical functions of digital control circuit and its function modules, and develops a set of digital control circuit equipment based on Advanced RISC Machines (ARM) with typical function modules, including principle design, interference injection trace design, function design, and study the failure mode and threshold of typical function modules. Based on continuous wave (CW) and pulse wave, the direct power injection (DPI) method is used to test the conduction immunity of the digital control circuit, and the failure mode and sensitivity threshold of the digital control circuit are quantitatively obtained. This method can provide experimental verification for the immunity ability of the digital control circuit to different electromagnetic interference.

This paper presents on-chip characterization of electrostatic discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunctions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200mV were observed on the frontside when a 200-V ESD gun was irradiated through a 5kΩ contact resistor on the backside of a 350μm thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40μm, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.

We developed a self-controllable voltage level (SVL) circuit and applied this circuit to a single-power-supply, six-transistor complementary metal-oxide-semiconductor static random-access memory (SRAM) to not only improve both write and read performances but also to achieve low standby power and data retention (holding) capability. The SVL circuit comprises only three MOSFETs (i.e., pull-up, pull-down and bypass MOSFETs). The SVL circuit is able to adaptively generate both optimal memory cell voltages and word line voltages depending on which mode of operation (i.e., write, read or hold operation) was used. The write margin (VWM) and read margin (VRM) of the developed (dvlp) SRAM at a supply voltage (VDD) of 1V were 0.470 and 0.1923V, respectively. These values were 1.309 and 2.093 times VWM and VRM of the conventional (conv) SRAM, respectively. At a large threshold voltage (Vt) variability (=+6σ), the minimum power supply voltage (VMin) for the write operation of the conv SRAM was 0.37V, whereas it decreased to 0.22V for the dvlp SRAM. VMin for the read operation of the conv SRAM was 1.05V when the Vt variability (=-6σ) was large, but the dvlp SRAM lowered it to 0.41V. These results show that the SVL circuit expands the operating voltage range for both write and read operations to lower voltages. The dvlp SRAM reduces the standby power consumption (PST) while retaining data. The measured PST of the 2k-bit, 90-nm dvlp SRAM was only 0.957µW at VDD=1.0V, which was 9.46% of PST of the conv SRAM (10.12µW). The Si area overhead of the SVL circuits was only 1.383% of the dvlp SRAM.

Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

This paper summarizes the modulation configurations of phase locked loops (PLLs) and their integration in semiconductor circuits, e.g., the input modulation for cellular phones, direct-modulation for low power wireless sensor networks, feedback-loop modulation for high-speed transmission, and two-point modulation for short-range radio transceivers. In this survey, basic configuration examples of integrated circuits for wired and wireless applications which are using the PLL modulation configurations are explained. It is important to select the method for simply and effectively determining the characteristics corresponding to the specific application. The paper also surveys technologies for future PLL design for digitizing of an entire PLL to reduce the phase noise due to a modulation by using a feedback loop with a precise digital phase comparison and a numerically controlled oscillator with high linearity.

This article presents a 28GHz high-accuracy phase and amplitude detection circuit for dual-polarized phased-array calibration. With dual-polarized calibration scheme, external LO signal is not required for calibration. The proposed detection circuit detects phase and amplitude independently, using PDC and ADC. By utilizing a 28GHz-to-140kHz downconversion scheme, the phase and amplitude are detected more accurately. In addition, reference signal for PDC and ADC is generated from 28GHz LO signal with divide-by-6 dual-step-mixing injection locked frequency divider (ILFD). This ILFD achieves 24.5-32.5GHz (28%) locking range with only 3.0mW power consumption and 0.01mm2 area. In the measurement, the detection circuit achieves phase and amplitude detections with RMS errors of 0.17degree and 0.12dB, respectively. The total power consumption of the proposed circuit is 59mW with 1-V supply voltage.